[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)

Rename the function to reflect its correct behavior and to be consistent
with `Module::getOrInsertFunction`. This is a

[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)

Rename the function to reflect its correct behavior and to be consistent
with `Module::getOrInsertFunction`. This is also in preparation of
adding a new `Intrinsic::getDeclaration` that will have behavior similar
to `Module::getFunction` (i.e, just lookup, no creation).

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[VP] Kill VP_PROPERTY_(MEMOP,CASTOP) and simplify _CONSTRAINEDFP [nfc] (#105574)

These lists are quite static. Heavy use of macros is undesirable, and
not idiomatic in LLVM, so let's just use the n

[VP] Kill VP_PROPERTY_(MEMOP,CASTOP) and simplify _CONSTRAINEDFP [nfc] (#105574)

These lists are quite static. Heavy use of macros is undesirable, and
not idiomatic in LLVM, so let's just use the naive switch cases.

Note that the first two fields in the CONSTRAINEDFP property were
utterly unused (aside from a C++ test).

In the same vien as https://github.com/llvm/llvm-project/pull/105551.

Once both changes have landed, we'll be left with _BINARYOP which needs
a bit of additional untangling, and the actual opcode mappings.

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[VP] Refactor VectorBuilder to avoid layering violation. NFC (#99276)

This patch refactors the handling of reduction to eliminate layering
violations.

* Introduced `getReductionIntrinsicID` in L

[VP] Refactor VectorBuilder to avoid layering violation. NFC (#99276)

This patch refactors the handling of reduction to eliminate layering
violations.

* Introduced `getReductionIntrinsicID` in LoopUtils.h for mapping
recurrence kinds to llvm.vector.reduce.* intrinsic IDs.
* Updated `VectorBuilder::createSimpleTargetReduction` to accept
llvm.vector.reduce.* intrinsic directly.
* New function `VPIntrinsic::getForIntrinsic` for mapping intrinsic ID
to the same functional VP intrinsic ID.

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[VP][RISCV] Introduce vp.splat and RISC-V. (#98731)

This patch introduces a vp intrinsic for splat. It's helpful for
IR-level passes to create a splat with specific vector length.

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 8988148003

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 89881480030f48f83af668175b70a9798edca2fb.
This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.

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Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AAr

Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN.
RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86:
Returns NUM but not same with IEEE754-2019's minimumNumber as
+0.0 is not always greater than -0.0.
MIPS/LoongArch/Generic: return NUM.
LIBCALL: returns qNaN.

So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow
IEEE754-2019's minimumNumber/maximumNumber.

Half-fix: #93033

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[VP][RISCV] Add vp.reduce.fmaximum/fminimum and its RISC-V codegen (#91782)

`vp.reduce.fmaximum/fminimum` are the VP version of
`vector.reduce.fmaximum/fminimum`.

[VP] Fix unit test failures caused by #90502

Forgot to add vp.cttz.elts into the unittest. Also, I didn't specify the
positions of overloaded type parameters.

[VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (#82627)

RISC-V implements vector lrint/llrint by vfcvt.x.f.v.

[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. (#82370)

This patch also pick the MatchContext framework from DAGCombiner to an
indiviual header file to make the framew

[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. (#82370)

This patch also pick the MatchContext framework from DAGCombiner to an
indiviual header file to make the framework be used from other files in
llvm/lib/CodeGen/SelectionDAG/.

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[VP][RISCV] Introduce llvm.vp.minimum/maximum intrinsics (#74840)

Although there are predicated versions of minnum/maxnum, the ones for
minimum/maximum are currently missing. This patch introduces

[VP][RISCV] Introduce llvm.vp.minimum/maximum intrinsics (#74840)

Although there are predicated versions of minnum/maxnum, the ones for
minimum/maximum are currently missing. This patch introduces these
intrinsics and implements their lowering to RISC-V.

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[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)

This is similar to vector.reverse, but only reverses the first EVL
elements.

I extracted this code from our downstream. Some of it may have

[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)

This is similar to vector.reverse, but only reverses the first EVL
elements.

I extracted this code from our downstream. Some of it may have come from
https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi/ originally.

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[VP][RISCV] Add vp.is.fpclass and RISC-V support

There is no vp.fpclass after FCLASS_VL(D151176), try to support vp.fpclass.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D15

[VP][RISCV] Add vp.is.fpclass and RISC-V support

There is no vp.fpclass after FCLASS_VL(D151176), try to support vp.fpclass.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D152993

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[VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.abs/ctlz/cttz.

The patch ensures last two operands of vp.abs/ctlz/cttz are mask and evl.

Reviewed By: craig.topper

Differen

[VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.abs/ctlz/cttz.

The patch ensures last two operands of vp.abs/ctlz/cttz are mask and evl.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144536

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[VP][RISCV] Add vp.abs and RISC-V support.

RISC-V uses ISD::ABS lower method (abs x) -> (smax_vl x (sub_vl 0, x)) for ISD::VP_ABS.

Reviewed By: craig.topper

Differential Revision: https://reviews.

[VP][RISCV] Add vp.abs and RISC-V support.

RISC-V uses ISD::ABS lower method (abs x) -> (smax_vl x (sub_vl 0, x)) for ISD::VP_ABS.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D141033

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[VP][RISCV] Add vp.ctlz/cttz and RISC-V support.

The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes
and the cost model of vp.ctlz/cttz.

Reviewed By: craig.topper

Differ

[VP][RISCV] Add vp.ctlz/cttz and RISC-V support.

The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes
and the cost model of vp.ctlz/cttz.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140370

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[llvm] Use std::optional instead of Optional

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-ge

[llvm] Use std::optional instead of Optional

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716

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[llvm] llvm::Optional::value => operator*/operator->

std::optional::value() has undesired exception checking semantics and is
unavailable in some older Xcode. The call sites block std::optional migr

[llvm] llvm::Optional::value => operator*/operator->

std::optional::value() has undesired exception checking semantics and is
unavailable in some older Xcode. The call sites block std::optional migration.

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std::optional::value => operator*/operator->

value() has undesired exception checking semantics and calls
__throw_bad_optional_access in libc++. Moreover, the API is unavailable without
_LIBCPP_NO_E

std::optional::value => operator*/operator->

value() has undesired exception checking semantics and calls
__throw_bad_optional_access in libc++. Moreover, the API is unavailable without
_LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see
_LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS).

This fixes check-llvm.

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[VP][RISCV] Add vp.ctpop and RISC-V support.

The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org

[VP][RISCV] Add vp.ctpop and RISC-V support.

The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139920

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[VP][RISCV] Add vp.bitreverse and RISC-V support.

The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Reviewed By: craig.topper

Differential Revision: https://revi

[VP][RISCV] Add vp.bitreverse and RISC-V support.

The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139697

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[VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."

This reverts commit 7883e5b061bdbbe8bee5f479ebe911db5045b7e9.

The original commit was reverted that it didn't update test files after D13

[VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."

This reverts commit 7883e5b061bdbbe8bee5f479ebe911db5045b7e9.

The original commit was reverted that it didn't update test files after D136263
landed. The recommit fixed those.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139509

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Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."

This reverts commit 70de0e014013b4d97febe6704881a9a8c893d078.

I'm seeing:

Failed Tests (2):
LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr

Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."

This reverts commit 70de0e014013b4d97febe6704881a9a8c893d078.

I'm seeing:

Failed Tests (2):
LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Also reported at:

https://lab.llvm.org/buildbot/#/builders/123/builds/14531

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[VP][RISCV] Add vp.fshl/fshr and RISC-V support.

The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https:

[VP][RISCV] Add vp.fshl/fshr and RISC-V support.

The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379

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[IR] Use std::nullopt instead of None (NFC)

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-get

[IR] Use std::nullopt instead of None (NFC)

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716

show more ...