|
Revision tags: llvmorg-18.1.8 |
|
| #
4f54b918 |
| 14-Jun-2024 |
c8ef <c8ef@outlook.com> |
[SDPatternMatch] Only match ISD::SIGN_EXTEND in m_SExt (#95415)
Context: https://github.com/llvm/llvm-project/pull/95365#discussion_r1638236603
The current implementation of `m_SExt` matches both
[SDPatternMatch] Only match ISD::SIGN_EXTEND in m_SExt (#95415)
Context: https://github.com/llvm/llvm-project/pull/95365#discussion_r1638236603
The current implementation of `m_SExt` matches both `ISD::SIGN_EXTEND` and `ISD::SIGN_EXTEND_INREG`. However, in cases where we specifically need to match _only_ `ISD::SIGN_EXTEND`, such as in the SelectionDAG graph below, this can lead to issues and unintended combinations.
```
SelectionDAG has 13 nodes:
t0: ch,glue = EntryToken
t2: v2i32,ch = CopyFromReg t0, Register:v2i32 %0
t21: v2i32 = sign_extend_inreg t2, ValueType:ch:v2i8
t4: v2i32,ch = CopyFromReg t0, Register:v2i32 %1
t22: v2i32 = sign_extend_inreg t4, ValueType:ch:v2i8
t23: v2i32 = avgfloors t21, t22
t24: v2i32 = sign_extend_inreg t23, ValueType:ch:v2i8
t15: ch,glue = CopyToReg t0, Register:v2i32 $d0, t24
t16: ch = AArch64ISD::RET_GLUE t15, Register:v2i32 $d0, t15:1
```
show more ...
|
|
Revision tags: llvmorg-18.1.7, llvmorg-18.1.6 |
|
| #
0638e222 |
| 02-May-2024 |
Min-Yih Hsu <min.hsu@sifive.com> |
[SDPatternMatch] Add m_CondCode, m_NoneOf, and some SExt improvements (#90762)
- Add m_CondCode to match the ISD::CondCode value from CondCodeSDNode
- Add m_NoneOf combinator
- m_SExt now re
[SDPatternMatch] Add m_CondCode, m_NoneOf, and some SExt improvements (#90762)
- Add m_CondCode to match the ISD::CondCode value from CondCodeSDNode
- Add m_NoneOf combinator
- m_SExt now recognizes sext_inreg
show more ...
|
|
Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
|
| #
17af9add |
| 20-Mar-2024 |
Marc Auberer <marc.auberer@chillibits.com> |
[DAG] Add SDPatternMatch m_ZExtOrSelf/m_SExtOrSelf/m_AExtOrSelf/m_TruncOrSelf matchers (#85480)
Fixes #85395
|
|
Revision tags: llvmorg-18.1.2 |
|
| #
bc70f604 |
| 18-Mar-2024 |
zicwangupa <87221359+ZiCong-Wang@users.noreply.github.com> |
[SelectionDAG] Add m_Neg and m_Not pattern matcher and update DAGCombiner (#85365)
Resolves #85065
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
|
| #
c9c23261 |
| 14-Mar-2024 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[DAG] Add SDPatternMatch m_SMin/m_SMax/m_UMin/m_UMax matchers
|
| #
560d7c51 |
| 13-Mar-2024 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[DAG] Add SDPatternMatch m_And/m_Or/m_Xor matchers for logic ops
|
|
Revision tags: llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4 |
|
| #
5874874c |
| 23-Feb-2024 |
Min-Yih Hsu <min.hsu@sifive.com> |
[SelectionDAG] Introducing the SelectionDAG pattern matching framework (#78654)
Akin to `llvm::PatternMatch` and `llvm::MIPatternMatch`, the
`llvm::SDPatternMatch` introduced in this patch provides
[SelectionDAG] Introducing the SelectionDAG pattern matching framework (#78654)
Akin to `llvm::PatternMatch` and `llvm::MIPatternMatch`, the
`llvm::SDPatternMatch` introduced in this patch provides a DSL-alike
framework to match SDValue / SDNode with a more succinct syntax.
show more ...
|