[DAG] Add SDPatternMatch::m_BitCast matcher (#123327)

Simplifies a future patch

[SDPatternMatch] Add Matcher m_Undef (#122521)

Add Matcher `m_Undef`

Fixes: #122439

[SDPatternMatch] Add matchers m_ExtractSubvector and m_InsertSubvector (#120212)

Fixes #118846

Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (#119592)

This PR resolves #118845. I aimed to mirror the implementation
`m_Shuffle()` in
[PatternMatch.h](https://github.com/llvm/ll

Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (#119592)

This PR resolves #118845. I aimed to mirror the implementation
`m_Shuffle()` in
[PatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/PatternMatch.h).

Updated
[SDPatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/CodeGen/SDPatternMatch.h)
- Added `struct m_Mask` to match masks (`ArrayRef<int>`)
- Added two `m_Shuffle` functions. One to match independently of mask,
and one to match considering mask.
- Added `struct SDShuffle_match` to match `ISD::VECTOR_SHUFFLE`
considering mask

Updated
[SDPatternMatchTest.cpp](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp)
- Added `matchVecShuffle` test, which tests the behavior of both
`m_Shuffle()` functions

- - -

I am not sure if my test coverage is complete. I am not sure how to test
a `false` match, simply test against a different instruction? [Other
tests
](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp#L175),
such as for `VSelect`, test against `Select`. I am not sure if there is
an analogous instruction to compare against for `VECTOR_SHUFFLE`. I
would appreciate some pointers in this area. In general, please
liberally critique this PR!

---------

Co-authored-by: Aidan <aidan.goldfarb@mail.mcgill.ca>

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[DAG] SDPatternMatch - Add m_ExtractElt and m_InsertElt matchers (#119430)

Resolves #118844

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks

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[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)

This patch allows using enumeration values directly and simplifies the
implementation with bitwise logic. It addresses the comment in
htt

[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)

This patch allows using enumeration values directly and simplifies the
implementation with bitwise logic. It addresses the comment in
https://github.com/llvm/llvm-project/pull/113808#discussion_r1819923625.

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[DAG] SDPatternMatch - add missing ROTL/ROTR matchers

[DAG] SDPatternMatch - add missing BSWAP/CTPOP/CTTZ matchers

Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)

This patch adds icmp+select patterns for integer min/max matcher

Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)

This patch adds icmp+select patterns for integer min/max matchers in
SDPatternMatch, similar to those in IR PatternMatch.

Reapply #111774.

Closes #108218.

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Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112200)

Reverts llvm/llvm-project#111774

This appears to be causing so

Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112200)

Reverts llvm/llvm-project#111774

This appears to be causing some tests to fail.

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[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes. (#111774)

Closes #108218.

This patch adds icmp+select patterns for integer min/ma

[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes. (#111774)

Closes #108218.

This patch adds icmp+select patterns for integer min/max matchers in
SDPatternMatch, similar to those in IR PatternMatch.

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[DAGCombine] Count leading ones: refine post DAG/Type Legalisation if promotion (#102877)

This PR is related to #99591. In this PR, instead of modifying how the
legalisation occurs depending on sur

[DAGCombine] Count leading ones: refine post DAG/Type Legalisation if promotion (#102877)

This PR is related to #99591. In this PR, instead of modifying how the
legalisation occurs depending on surrounding instructions, we refine
after legalisation.

This PR has two parts:

* `SDPatternMatch/MatchContext`: Modify a little bit the code to match
Operands (used by `m_Node(...)`) and Unary/Binary/Ternary Patterns to
make it compatible with `VPMatchContext`, instead of only `m_Opc`
supported. Some tests were added to ensure no regressions.
* `DAGCombiner`: Add a `foldSubCtlzNot` which detect and rewrite the
patterns using matching context.

Remaining Tasks:

- [ ] GlobalISel
- [ ] Currently the pattern matching will occur even before
legalisation. Should I restrict it to specific stages instead ?
- [ ] Style: Add a visitVP_SUB ?? Move `foldSubCtlzNot` in another
location for style consistency purpose ?

@topperc

---------

Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>

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[DAG][PatternMatch] Add support for matchers with flags; NFC

Add support for matching with `SDNodeFlags` i.e `add` with `nuw`.

This patch adds helpers for `or disjoint` or `zext nneg` with the same

[DAG][PatternMatch] Add support for matchers with flags; NFC

Add support for matching with `SDNodeFlags` i.e `add` with `nuw`.

This patch adds helpers for `or disjoint` or `zext nneg` with the same
names as we have in IR/PatternMatch api.

Closes #103060

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[DAG] SD Pattern Match: Operands patterns with VP Context (#103308)

Currently, when using a VP match context with `sd_context_match`, only Opcode matching is possible (`m_Opc(Opcode)`).

This PR

[DAG] SD Pattern Match: Operands patterns with VP Context (#103308)

Currently, when using a VP match context with `sd_context_match`, only Opcode matching is possible (`m_Opc(Opcode)`).

This PR suggest a way to make patterns with Operands (eg `m_Node`, `m_Add`, ...) works with a VP context.

This PR blocks another PR https://github.com/llvm/llvm-project/pull/102877.

Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>

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[DAG] Adding m_FPToUI and m_FPToSI to SDPatternMatch.h (#104044)

Adds m_FPToUI/m_FPToSI matchers for ISD::FP_TO_UINT/ISD::FP_TO_SINT in SDPatternMatch.h with suitable test coverage.

Fixes https:/

[DAG] Adding m_FPToUI and m_FPToSI to SDPatternMatch.h (#104044)

Adds m_FPToUI/m_FPToSI matchers for ISD::FP_TO_UINT/ISD::FP_TO_SINT in SDPatternMatch.h with suitable test coverage.

Fixes https://github.com/llvm/llvm-project/issues/103872

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[DAG] Add SDPatternMatch::m_VSelect (#100758)

As per the comment in
https://github.com/llvm/llvm-project/pull/100686#pullrequestreview-2201991135

[DAG] Add SDPatternMatch for VScale nodes

[DAG] Add SDPatternMatch::m_Select (#100686)

This will enable us to use SDPatternMatch with ISD::SELECT SDNodes in
the future.

CodeGen: Remove MachineModuleInfo reference from MachineFunction (#100357)

This avoids another unserializable field. Move the DbgInfoAvailable
field into the AsmPrinter, which is only really a cache

CodeGen: Remove MachineModuleInfo reference from MachineFunction (#100357)

This avoids another unserializable field. Move the DbgInfoAvailable
field into the AsmPrinter, which is only really a cache/convenience
bit for checking a direct IR module metadata check.

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Reland "SelectionDAG: Avoid using MachineFunction::getMMI" (#99779)

Reverts llvm/llvm-project#99777

Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>

Revert "SelectionDAG: Avoid using MachineFunction::getMMI" (#99777)

Reverts llvm/llvm-project#99696

https://lab.llvm.org/buildbot/#/builders/164/builds/1262

SelectionDAG: Avoid using MachineFunction::getMMI (#99696)

[DAG] Add SDPatternMatch::m_SetCC and update some combines to use it (#98646)

The plan is to add more TernaryOp in the future (SELECT/VSELECT and FMA in particular)

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

Replace it with a forward declaration instead. Analysis.h is pulled in
by all passes, but not all passes need to access the module.