Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6 |
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1562b70e |
| 13-Dec-2024 |
paperchalice <liujunchang97@outlook.com> |
Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119547)
This relands commit #115111.
Use traditional way to update post dominator tree, i.e. break critical
edge splitting
Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119547)
This relands commit #115111.
Use traditional way to update post dominator tree, i.e. break critical
edge splitting into insert, insert, delete sequence.
When splitting critical edges, the post dominator tree may change its
root node, and `setNewRoot` only works in normal dominator tree...
See
https://github.com/llvm/llvm-project/blob/6c7e5827eda26990e872eb7c3f0d7866ee3c3171/llvm/include/llvm/Support/GenericDomTree.h#L684-L687
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553058f8 |
| 11-Dec-2024 |
paperchalice <liujunchang97@outlook.com> |
Revert "[DomTreeUpdater] Move critical edge splitting code to updater" (#119512)
Reverts llvm/llvm-project#115111 Causes #119511
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79047fac |
| 11-Dec-2024 |
paperchalice <liujunchang97@outlook.com> |
[DomTreeUpdater] Move critical edge splitting code to updater (#115111)
Support critical edge splitting in dominator tree updater. Continue the
work in #100856.
Compile time check:
https://llvm
[DomTreeUpdater] Move critical edge splitting code to updater (#115111)
Support critical edge splitting in dominator tree updater. Continue the
work in #100856.
Compile time check:
https://llvm-compile-time-tracker.com/compare.php?from=87c35d782795b54911b3e3a91a5b738d4d870e55&to=42b3e5623a9ab4c3648564dc0926b36f3b438a3a&stat=instructions%3Au
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Revision tags: llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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6a907699 |
| 11-Jul-2024 |
Nikita Popov <npopov@redhat.com> |
Revert "[CodeGen] Remove `applySplitCriticalEdges` in `MachineDominatorTree` (#97055)"
This reverts commit c5e5088033fed170068d818c54af6862e449b545.
Causes large compile-time regressions.
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c5e50880 |
| 11-Jul-2024 |
paperchalice <liujunchang97@outlook.com> |
[CodeGen] Remove `applySplitCriticalEdges` in `MachineDominatorTree` (#97055)
Summary:
- Remove wrappers in `MachineDominatorTree`.
- Remove `MachineDominatorTree` update code in
`MachineBasicBlo
[CodeGen] Remove `applySplitCriticalEdges` in `MachineDominatorTree` (#97055)
Summary:
- Remove wrappers in `MachineDominatorTree`.
- Remove `MachineDominatorTree` update code in
`MachineBasicBlock::SplitCriticalEdge`.
- Use `MachineDomTreeUpdater` in passes which call
`MachineBasicBlock::SplitCriticalEdge` and preserve
`MachineDominatorTreeWrapperPass` or CFG analyses.
Commit abea99f65a97248974c02a5544eaf25fc4240056 introduced related
methods in 2014. Now we have SemiNCA based dominator tree in 2017 and
dominator tree updater, the solution adopted here seems a bit outdated.
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Revision tags: llvmorg-18.1.8 |
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837dc542 |
| 11-Jun-2024 |
paperchalice <liujunchang97@outlook.com> |
[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)
Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree v
[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)
Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree version of `DomTreeUpdater` to
handle `SplitCriticalEdge` in some CodeGen passes.
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Revision tags: llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init |
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333ffafb |
| 14-Jan-2023 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Trim includes and avoid using namespace in a header
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79858d19 |
| 14-Jan-2023 |
Craig Topper <craig.topper@sifive.com> |
[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
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Revision tags: llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3 |
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2592ccde |
| 18-Oct-2022 |
Arthur Eubanks <aeubanks@google.com> |
[llvm-reduce] Unify pass logging
We randomly use outs() or errs(), which makes test logs confusing. We also randomly add/don't add a line afterward.
Reviewed By: arsenm
Differential Revision: http
[llvm-reduce] Unify pass logging
We randomly use outs() or errs(), which makes test logs confusing. We also randomly add/don't add a line afterward.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136130
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Revision tags: working, llvmorg-15.0.2, llvmorg-15.0.1 |
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c9ef7d49 |
| 14-Sep-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Do not insert replacement IMPLICIT_DEFs for dead defs
Also skip dead defs when looking for a previous vreg with the same class. This helps avoid some mid-reduction verifier errors when
llvm-reduce: Do not insert replacement IMPLICIT_DEFs for dead defs
Also skip dead defs when looking for a previous vreg with the same class. This helps avoid some mid-reduction verifier errors when LiveIntervals computation starts introducing dead flags everywhere.
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78865050 |
| 13-Sep-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Add undef to new subregister IMPLICIT_DEFs
This avoids a verifier error from the other unused lanes when LiveIntervals is used.
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Revision tags: llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5 |
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e6723d80 |
| 04-Jun-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Fix crashes on unreachable blocks for MIR instructions
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42c7f494 |
| 03-Jun-2022 |
Clemens Wasser <clemens.wasser@gmail.com> |
[tools] Forward declare classes & remove includes
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D120208
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Revision tags: llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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241ca47d |
| 19-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Reduce includes
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aabea3b2 |
| 19-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Fix not removing first instruction in MachineBasicBlock
This had the surprising behavior of using whatever instruction happened to be first in the block as an anchor point to stick rand
llvm-reduce: Fix not removing first instruction in MachineBasicBlock
This had the surprising behavior of using whatever instruction happened to be first in the block as an anchor point to stick random implicit defs on. Use a real implicit_def instead.
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0b896b75 |
| 25-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Do not try to delete frame instructions
The verifier enforces these appearing as balanced pairs, so just deleting one has no real chance of producing something valid.
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7c2db666 |
| 19-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Support multiple MachineFunctions
The current testcase I'm trying to reduce only reproduces with IPRA enabled and requires handling multiple functions.
The only real difference vs. the
llvm-reduce: Support multiple MachineFunctions
The current testcase I'm trying to reduce only reproduces with IPRA enabled and requires handling multiple functions.
The only real difference vs. the IR is the extra indirect to look for the underlying MachineFunction, so treat the ReduceWorkItem as the module instead of the function.
The ugliest piece of this is really the ugliness of MachineModuleInfo. It not only tracks actual module state, but has a number of transient fields used for isel and/or the asm printer. These shouldn't do any harm for the use here, though they should be separated out.
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e617d1a1 |
| 19-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Fix mangling types of generic registers
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6d6288f2 |
| 19-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Preserve subregisters and other fields for top block def
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a0f9e4ed |
| 13-Apr-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
llvm-reduce: Fix handling of generic virtual registers
Try to preserve register banks, types and names. Fixes the lowest hanging fruit in issue 54894.
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Revision tags: llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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6f288bd7 |
| 12-Nov-2021 |
Arthur Eubanks <aeubanks@google.com> |
[llvm-reduce] Count chunks by running a preliminary reduction
Having a separate counting method runs the risk of a mismatch between the actual reduction method and the counting method.
Instead, cre
[llvm-reduce] Count chunks by running a preliminary reduction
Having a separate counting method runs the risk of a mismatch between the actual reduction method and the counting method.
Instead, create an Oracle that always returns true for shouldKeep(), run the reduction, and count how many times shouldKeep() was called. The module should not be modified if shouldKeep() always returns true.
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D113537
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fd41738e |
| 02-Nov-2021 |
Markus Lavin <markus.lavin@ericsson.com> |
Recommit "[llvm-reduce] Add MIR support"
(Second try. Need to link against CodeGen and MC libs.)
The llvm-reduce tool has been extended to operate on MIR (import, clone and export). Current limitat
Recommit "[llvm-reduce] Add MIR support"
(Second try. Need to link against CodeGen and MC libs.)
The llvm-reduce tool has been extended to operate on MIR (import, clone and export). Current limitation is that only a single machine function is supported. A single reducer pass that operates on machine instructions (while on SSA-form) has been added. Additional MIR specific reducer passes can be added later as needed.
Differential Revision: https://reviews.llvm.org/D110527
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bc2773cb |
| 02-Nov-2021 |
Markus Lavin <markus.lavin@ericsson.com> |
[llvm-reduce] Add MIR support
The llvm-reduce tool has been extended to operate on MIR (import, clone and export). Current limitation is that only a single machine function is supported. A single re
[llvm-reduce] Add MIR support
The llvm-reduce tool has been extended to operate on MIR (import, clone and export). Current limitation is that only a single machine function is supported. A single reducer pass that operates on machine instructions (while on SSA-form) has been added. Additional MIR specific reducer passes can be added later as needed.
Differential Revision: https://reviews.llvm.org/D110527
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