|
Revision tags: llvmorg-21-init |
|
| #
ff1b01bb |
| 16-Jan-2025 |
Craig Topper <craig.topper@sifive.com> |
[llvm-exegesis] Begin replacing unsigned with MCRegister. NFC (#123109)
Some of this was needed to fix implicit conversions from MCRegister to
unsigned when calling getReg() on MCOperand for exampl
[llvm-exegesis] Begin replacing unsigned with MCRegister. NFC (#123109)
Some of this was needed to fix implicit conversions from MCRegister to
unsigned when calling getReg() on MCOperand for example.
The majority was done by reviewing parts of the code that dealt with
registers, converting them to MCRegister and then seeing what new
implicit conversions were created and fixing those.
There were a few places where I used MCPhysReg instead of MCRegiser for
static arrays since its uint16_t instead of unsigned.
show more ...
|
|
Revision tags: llvmorg-19.1.7 |
|
| #
8e8692a5 |
| 18-Dec-2024 |
Bushev Dmitry <111585886+dybv-sc@users.noreply.github.com> |
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120467)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
regist
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120467)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
registers used as memory address in instruction.
* Added scratch memory space pointer register.
* General exegesis options were amended:
* mattr - new option to pass a list of enabled target features
Llvm-exegesis RISCV port is a result of team effort. Below everyone
involved listed.
Co-authored-by: Konstantin Vladimirov
<konstantin.vladimirov@syntacore.com>
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com>
Co-authored-by: Anastasiya Chernikova
<anastasiya.chernikova@syntacore.com>
Original pr: #89047
---------
Co-authored-by: Kazu Hirata <kazu@google.com>
show more ...
|
| #
08849083 |
| 18-Dec-2024 |
Thurston Dang <thurston@google.com> |
Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)"
This reverts commit 6993d32c77a78ac0e6eee0e4bffd714a455e776b.
Reason: buildbot breakage
(https://lab.llvm.org/buildbot/#/bui
Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)"
This reverts commit 6993d32c77a78ac0e6eee0e4bffd714a455e776b.
Reason: buildbot breakage
(https://lab.llvm.org/buildbot/#/builders/51/builds/7908)
CCACHE_CPP2=yes CCACHE_HASHDIR=yes /usr/bin/ccache /home/b/sanitizer-aarch64-linux/build/llvm_build0/bin/clang++ -DGTEST_HAS_RTTI=0 -DLLVM_BUILD_STATIC -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/b/sanitizer-aarch64-linux/build/build_default/tools/llvm-exegesis/lib/RISCV -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV -I/home/b/sanitizer-aarch64-linux/build/build_default/include -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/include -I/home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/lib/Target/RISCV -I/home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -MD -MT tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o -MF tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o.d -o tools/llvm-exegesis/lib/RISCV/CMakeFiles/LLVMExegesisRISCV.dir/Target.cpp.o -c /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
In file included from /home/b/sanitizer-aarch64-linux/build/llvm-project/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp:139:
/home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV/RISCVGenAsmMatcher.inc:239:19: error: unused function 'MatchRegisterName' [-Werror,-Wunused-function]
239 | static MCRegister MatchRegisterName(StringRef Name) {
| ^~~~~~~~~~~~~~~~~
/home/b/sanitizer-aarch64-linux/build/build_default/lib/Target/RISCV/RISCVGenAsmMatcher.inc:568:19: error: unused function 'MatchRegisterAltName' [-Werror,-Wunused-function]
568 | static MCRegister MatchRegisterAltName(StringRef Name) {
| ^~~~~~~~~~~~~~~~~~~~
show more ...
|
| #
6993d32c |
| 18-Dec-2024 |
Bushev Dmitry <111585886+dybv-sc@users.noreply.github.com> |
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
regist
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
registers used as memory address in instruction.
* Added scratch memory space pointer register.
* General exegesis options were amended:
* mattr - new option to pass a list of enabled target features
Llvm-exegesis RISCV port is a result of team effort. Below everyone
involved listed.
Co-authored-by: Konstantin Vladimirov
<konstantin.vladimirov@syntacore.com>
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com>
Co-authored-by: Anastasiya Chernikova
<anastasiya.chernikova@syntacore.com>
---------
Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
show more ...
|
| #
bf62ea40 |
| 18-Dec-2024 |
Wang Pengcheng <wangpengcheng.pp@bytedance.com> |
Revert "[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)"
This reverts commit bc3eee11ea6f771bf007c4921a34c1dfee040471.
These tests are failing because of no `REQUIRES`.
|
| #
bc3eee11 |
| 18-Dec-2024 |
AnastasiyaChernikova <anastasiya.chernikova@syntacore.com> |
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
registe
[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#89047)
This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
registers used as memory address in instruction.
* Added scratch memory space pointer register.
* General exegesis options were amended:
* mattr - new option to pass a list of enabled target features
Llvm-exegesis RISCV port is a result of team effort. Below everyone
involved listed.
Co-authored-by: Konstantin Vladimirov
<konstantin.vladimirov@syntacore.com>
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com>
Co-authored-by: Anastasiya Chernikova
<anastasiya.chernikova@syntacore.com>
---------
Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
show more ...
|
|
Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1 |
|
| #
faf675ce |
| 29-Jan-2024 |
Aiden Grossman <agrossman154@yahoo.com> |
[llvm-exegesis] Remove llvm prefix where unnecessary (#79802)
This patch removes the llvm:: prefix within llvm-exegesis where it is
not necessary. This is most occurrences of the prefix within exeg
[llvm-exegesis] Remove llvm prefix where unnecessary (#79802)
This patch removes the llvm:: prefix within llvm-exegesis where it is
not necessary. This is most occurrences of the prefix within exegesis as
exegesis is within the llvm namespace. This patch makes things more
consistent as the vast majority of the code did not use the llvm::
prefix for anything.
show more ...
|
|
Revision tags: llvmorg-19-init |
|
| #
3b1761b8 |
| 03-Dec-2023 |
Kazu Hirata <kazu@google.com> |
[llvm] Stop including map (NFC)
Identified with clangd.
|
|
Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
|
| #
073401e5 |
| 11-Jan-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere
instead of getImplicitUses, getNumImplicitUses, getImpl
[MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere
instead of getImplicitUses, getNumImplicitUses, getImplicitDefs and
getNumImplicitDefs. A future patch will remove the old methods.
In some use cases the new methods are less efficient because they always
have to scan the whole uses/defs array to count its length, but that
will be fixed in a future patch by storing the number of implicit
uses/defs explicitly in MCInstrDesc. At that point there will be no need
to 0-terminate the arrays.
Differential Revision: https://reviews.llvm.org/D142215
show more ...
|
| #
768aed13 |
| 13-Jan-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A futu
[MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use
it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end.
A future patch will remove opInfo_begin and opInfo_end.
Also use it instead of raw access to the OpInfo pointer. A future patch
will remove this pointer.
Differential Revision: https://reviews.llvm.org/D142213
show more ...
|
| #
a5b56313 |
| 20-Dec-2022 |
Roman Lebedev <lebedev.ri@gmail.com> |
[llvm-exegesis] `AliasingConfigurations`: pay attention to forbidden registers
When trying to measure latency of certain opcodes, e.g.
`./bin/llvm-exegesis --opcode-name=BT32ri8 --mode=latency --rep
[llvm-exegesis] `AliasingConfigurations`: pay attention to forbidden registers
When trying to measure latency of certain opcodes, e.g.
`./bin/llvm-exegesis --opcode-name=BT32ri8 --mode=latency --repetition-mode=loop --benchmarks-file=- --max-configs-per-opcode=65536`,
we'd pick such an aliasing instruction, and such an aliasing registers,
that would alias with forbidden registers.
And in particular with loop counter in `loop` repetition mode,
which made the measurements never finish.
This does not address all such cases, only the most obvious one.
The added test case fails without the patch.
Fixes https://github.com/llvm/llvm-project/issues/59441
show more ...
|
|
Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
|
| #
a81b64a1 |
| 26-Jun-2022 |
Kazu Hirata <kazu@google.com> |
[llvm] Use Optional::has_value instead of Optional::hasValue (NFC)
This patch replaces x.hasValue() with x.has_value() where x is not
contextually convertible to bool.
|
| #
3b7c3a65 |
| 25-Jun-2022 |
Kazu Hirata <kazu@google.com> |
Revert "Don't use Optional::hasValue (NFC)"
This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.
|
| #
aa8feeef |
| 25-Jun-2022 |
Kazu Hirata <kazu@google.com> |
Don't use Optional::hasValue (NFC)
|
|
Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
|
| #
698c6b0a |
| 05-Feb-2021 |
Dan Gohman <dev@sunfishcode.online> |
[WebAssembly] Support single-floating-point immediate value
As mentioned in TODO comment, casting double to float causes NaNs to change bits.
To avoid the change, this patch adds support for single-
[WebAssembly] Support single-floating-point immediate value
As mentioned in TODO comment, casting double to float causes NaNs to change bits.
To avoid the change, this patch adds support for single-floating-point immediate value on MachineCode.
Patch by Yuta Saito.
Differential Revision: https://reviews.llvm.org/D77384
show more ...
|
|
Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2 |
|
| #
83d0db59 |
| 04-Feb-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
Fix "expression is redundant [misc-redundant-expression]" warning (PR44768)
Be more specific that getOperandConstraint should return -1 or a uint8_t value
|
|
Revision tags: llvmorg-10.0.0-rc1, llvmorg-11-init |
|
| #
09db6e32 |
| 14-Jan-2020 |
Jonas Devlieghere <jonas@devlieghere.com> |
[llvm-exegesis] Initialize const bitvector member
This causes an error with older versions of clang: constructor for
'llvm::exegesis::InstructionsCache' must explicitly initialize the const
member '
[llvm-exegesis] Initialize const bitvector member
This causes an error with older versions of clang: constructor for
'llvm::exegesis::InstructionsCache' must explicitly initialize the const
member 'BVC'
show more ...
|
| #
32d384c0 |
| 18-Dec-2019 |
Guillaume Chatelet <gchatelet@google.com> |
[llvm-exegesis][NFC] internal changes
Summary:
BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.
Reviewers: courbet
Subscribers: sdardis, tschuett, jrtc
[llvm-exegesis][NFC] internal changes
Summary:
BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.
Reviewers: courbet
Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71653
show more ...
|
|
Revision tags: llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1 |
|
| #
50cdd56b |
| 09-Oct-2019 |
Clement Courbet <courbet@google.com> |
[llvm-exegesis][NFC] Remove extra `llvm::` qualifications.
Summary: Second patch: in the lib.
Reviewers: gchatelet
Subscribers: nemanjai, tschuett, MaskRay, mgrang, jsji, llvm-commits
Tags: #llvm
[llvm-exegesis][NFC] Remove extra `llvm::` qualifications.
Summary: Second patch: in the lib.
Reviewers: gchatelet
Subscribers: nemanjai, tschuett, MaskRay, mgrang, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68692
llvm-svn: 374158
show more ...
|
| #
8ef97e1a |
| 27-Sep-2019 |
Clement Courbet <courbet@google.com> |
[llvm-exegesis] Refactor how forbidden registers are computed.
Summary:
Right now latency generation can incorrectly select the scratch register
as a dependency-carrying register.
- Move the logic
[llvm-exegesis] Refactor how forbidden registers are computed.
Summary:
Right now latency generation can incorrectly select the scratch register
as a dependency-carrying register.
- Move the logic for preventing register selection from Uops
implementation to common SnippetGenerator class.
- Aliasing detection now takes a set of forbidden registers just like
random register assignment does.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68084
llvm-svn: 373048
show more ...
|
| #
06f9ce84 |
| 26-Sep-2019 |
Clement Courbet <courbet@google.com> |
[llvm-exegesis][NFC] Remove dead code.
Summary: `hasAliasingImplicitRegistersThrough()` is no longer used.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Tags: #llvm
Differential Revis
[llvm-exegesis][NFC] Remove dead code.
Summary: `hasAliasingImplicitRegistersThrough()` is no longer used.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68078
llvm-svn: 372968
show more ...
|
|
Revision tags: llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1 |
|
| #
2946cd70 |
| 19-Jan-2019 |
Chandler Carruth <chandlerc@gmail.com> |
Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the ne
Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351636
show more ...
|
|
Revision tags: llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1 |
|
| #
da11b856 |
| 24-Oct-2018 |
Guillaume Chatelet <gchatelet@google.com> |
[llvm-exegesis] Implements a cache of Instruction objects.
llvm-svn: 345130
|
| #
32401afd |
| 22-Oct-2018 |
Fangrui Song <maskray@google.com> |
[llvm-exegesis] Move namespace exegesis inside llvm::
Summary:
This allows simplifying references of llvm::foo with foo when the needs
come in the future.
Reviewers: courbet, gchatelet
Reviewed By
[llvm-exegesis] Move namespace exegesis inside llvm::
Summary:
This allows simplifying references of llvm::foo with foo when the needs
come in the future.
Reviewers: courbet, gchatelet
Reviewed By: gchatelet
Subscribers: javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53455
llvm-svn: 344922
show more ...
|
| #
2e83b2e9 |
| 19-Oct-2018 |
Fangrui Song <maskray@google.com> |
Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC
llvm-svn: 344774
|