[LoopVectorize][NFC] Disable output for tests that don't need it (#124747)

There are a lot of tests that do not depend upon the IR output
for validation, relying instead on the debug output. For th

[LoopVectorize][NFC] Disable output for tests that don't need it (#124747)

There are a lot of tests that do not depend upon the IR output
for validation, relying instead on the debug output. For these
tests we can add the -disable-output command line argument.

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[LV] Reland "Update logic for calculating register usage due to invariants"

Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of wide

[LV] Reland "Update logic for calculating register usage due to invariants"

Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of widening
instructions. This resulted in calculating vector register types for vectors which cant be legalized(check the newly added test for more details).

An invariant might not always need a vector register. For e.g., invariant might just be used for iteration check.

This patch checks if the invariant is part of any widening instruction and considers register usage accordingly. Fixes issue 60493

Differential Revision: https://reviews.llvm.org/D143422

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Revert "[LV] Update logic for calculating register usage due to invariants"

Observing test failure for llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll

This reverts commit d1628266946fdddb44

Revert "[LV] Update logic for calculating register usage due to invariants"

Observing test failure for llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll

This reverts commit d1628266946fdddb44bdad2b3ccf3cd5fc769f42.

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[LV] Update logic for calculating register usage due to invariants

Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of widening
inst

[LV] Update logic for calculating register usage due to invariants

Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of widening
instructions. This resulted in calculating vector register types for vectors which cant be legalized(check the newly added test for more details).

An invariant might not always need a vector register. For e.g., invariant might just be used for iteration check.

This patch checks if the invariant is part of any widening instruction and considers register usage accordingly. Fixes issue 60493

Differential Revision: https://reviews.llvm.org/D143422

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[LoopVectorize] Convert some tests to opaque pointers (NFC)

Check lines for some of these tests were regenerated. The difference
is that with opaque pointers SCEVExpander always emits i8 GEPs,
makin

[LoopVectorize] Convert some tests to opaque pointers (NFC)

Check lines for some of these tests were regenerated. The difference
is that with opaque pointers SCEVExpander always emits i8 GEPs,
making the address calculation explicit. This is a known problem
that will be solved long term by making all address calculations
explicit.

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[NFC] Port all runlines for LoopVectorize pass tests to -passes syntax

[RISCV] Correct RISCVTTIImpl::getRegUsageForType for vectors of pointers.

getPrimitiveSizeInBits returns 0 for pointers, we need to query
the size via DataLayout instead.

Reviewed By: reames

Diffe

[RISCV] Correct RISCVTTIImpl::getRegUsageForType for vectors of pointers.

getPrimitiveSizeInBits returns 0 for pointers, we need to query
the size via DataLayout instead.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135976

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[RISCV] Define risc-v's own register class to model FP Register.

The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This hel

[RISCV] Define risc-v's own register class to model FP Register.

The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D126854

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Revert "[NFCI] Regenerate SROA/LoopVectorize test checks"

This reverts commit 14e3450fb57305aa9ff3e9e60687b458e43835c9.

[NFCI] Regenerate LoopVectorize test checks

[RISCV] Remove experimental prefix from rvv-related extensions.

Extensions affected: +v, +zve*, +zvl*

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117860

[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters

Those two TTI hooks are used during vectorization for calculating
register pressure, the default implementation isn't cons

[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters

Those two TTI hooks are used during vectorization for calculating
register pressure, the default implementation isn't consider for LMUL,
and that's also definitly wrong value for register number (all register class
are 8 registers).

So in this patch we tried to:

1. Calculate right register usage for vector type and scalar type.
2. Return right number of register for general purpose register and
vector register.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D116890

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