[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

This brings the printing of scalable vector constant splats inline with
their fixed length counterparts.

[LLVM][IR] Teach constant integer binop folds about vector ConstantInts. (#115739)

The existing logic mostly works with the main changes being:
* Use getScalarSizeInBits instead of IntegerType::ge

[LLVM][IR] Teach constant integer binop folds about vector ConstantInts. (#115739)

The existing logic mostly works with the main changes being:
* Use getScalarSizeInBits instead of IntegerType::getBitWidth
* Use ConstantInt::get(Type* instead of ConstantInt::get(LLVMContext

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[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

[InstCombine] Add function attribute `instcombine-no-verify-fixpoint` (#113822)

This patch introduces a function attribute
`instcombine-no-verify-fixpoint` to avoids disabling fix-point
verificati

[InstCombine] Add function attribute `instcombine-no-verify-fixpoint` (#113822)

This patch introduces a function attribute
`instcombine-no-verify-fixpoint` to avoids disabling fix-point
verification for unrelated tests in the same file.
Address comment
https://github.com/llvm/llvm-project/pull/112642#discussion_r1804714387.

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[InstCombine] Teach takeLog2 about right shifts, truncation and bitwise-and

We left some easy opportunities for further simplifications.

log2(trunc(x)) is simply trunc(log2(x)). This is safe if we

[InstCombine] Teach takeLog2 about right shifts, truncation and bitwise-and

We left some easy opportunities for further simplifications.

log2(trunc(x)) is simply trunc(log2(x)). This is safe if we know that
trunc is NUW because it means that the truncation didn't drop any bits.
It is also safe if the caller is OK with zero as a possible answer.

log2(x >>u y) is simply `log2(x) - y`.

log2(x & y) is a funny one. It comes up when doing something like:
```
unsigned int f(unsigned int x, unsigned int y) {
unsigned char a = 1u << x;
return y / a;
}
```

LLVM would canonicalize this to:
```
%shl = shl nuw i32 1, %x
%conv1 = and i32 %shl, 255
%div = udiv i32 %y, %conv1
```

In cases like these, we can ignore the mask entirely.
This is equivalent to `y >> x`.

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[InstCombine] Remove some of the complexity-based canonicalization (#91185)

The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be can

[InstCombine] Remove some of the complexity-based canonicalization (#91185)

The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be canonicalized away. This is
indeed very useful to e.g. know that constants are always on the right.

However, this is only useful if the canonicalization is actually
reliable. This is the case for constants, but not for arguments: Moving
these to the right makes it look like the "more complex" expression is
guaranteed to be on the left, but this is not actually the case in
practice. It fails as soon as you replace the argument with another
instruction.

The end result is that it looks like things correctly work in tests,
while they actually don't. We use the "thwart complexity-based
canonicalization" trick to handle this in tests, but it's often a
challenge for new contributors to get this right, and based on the
regressions this PR originally exposed, we clearly don't get this right
in many cases.

For this reason, I think that it's better to remove this complexity
canonicalization. It will make it much easier to write tests for
commuted cases and make sure that they are handled.

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[InstSimplify] Fold all poison phi to poison instead of undef

[InstCombine] Propagate flags when folding consecutative shifts

When we fold `(shift (shift C0, x), C1)` we can propagate flags that
are common to both shifts.

Proofs: https://alive2.llvm.org/ce/z/

[InstCombine] Propagate flags when folding consecutative shifts

When we fold `(shift (shift C0, x), C1)` we can propagate flags that
are common to both shifts.

Proofs: https://alive2.llvm.org/ce/z/LkEzXD

Closes #94872

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[InstCombine] Add tests for propagating flags when folding consecutative shifts; NFC

[InstCombine] Add multi-use tests for shift-of-shift transform (NFC)

Also drop irrelevant function attributes from tests.

[InstCombine] Swap out range metadata to range attribute for cttz/ctlz/ctpop (#88776)

Since all optimizations that use range metadata now also handle range attribute, this patch replaces writes of

[InstCombine] Swap out range metadata to range attribute for cttz/ctlz/ctpop (#88776)

Since all optimizations that use range metadata now also handle range attribute, this patch replaces writes of
range metadata for call instructions to range attributes.

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[InstCombine] Infer nsw/nuw for trunc (#87910)

This patch adds support for inferring trunc's nsw/nuw flags.

[ValueTracking] Handle non-canonical operand order in `isImpliedCondICmps`

We don't always have canonical order here, so do it manually.

Closes #85575

[LLVM][tests/Transforms/InstCombine] Convert instances of ConstantExpr based splats to use splat().

This is mostly NFC but some output does change due to consistently
inserting into poison rather th

[LLVM][tests/Transforms/InstCombine] Convert instances of ConstantExpr based splats to use splat().

This is mostly NFC but some output does change due to consistently
inserting into poison rather than undef and using i64 as the index
type for inserts.

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[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)

This patch canonicalizes getelementptr instructions with constant
indices to use the `i8` source element type. This makes

[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)

This patch canonicalizes getelementptr instructions with constant
indices to use the `i8` source element type. This makes it easier for
optimizations to recognize that two GEPs are identical, because they
don't need to see past many different ways to express the same offset.

This is a first step towards
https://discourse.llvm.org/t/rfc-replacing-getelementptr-with-ptradd/68699.
This is limited to constant GEPs only for now, as they have a clear
canonical form, while we're not yet sure how exactly to deal with
variable indices.

The test llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll gives
two representative examples of the kind of optimization improvement we
expect from this change. In the first test SimplifyCFG can now realize
that all switch branches are actually the same. In the second test it
can convert it into simple arithmetic. These are representative of
common optimization failures we see in Rust.

Fixes https://github.com/llvm/llvm-project/issues/69841.

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[ValueTracking] Add dominating condition support in computeKnownBits() (#73662)

This adds support for using dominating conditions in computeKnownBits()
when called from InstCombine. The implementat

[ValueTracking] Add dominating condition support in computeKnownBits() (#73662)

This adds support for using dominating conditions in computeKnownBits()
when called from InstCombine. The implementation uses a
DomConditionCache, which stores which branches may provide information
that is relevant for a given value.

DomConditionCache is similar to AssumptionCache, but does not try to do
any kind of automatic tracking. Relevant branches have to be explicitly
registered and invalidated values explicitly removed. The necessary
tracking is done inside InstCombine.

The reason why this doesn't just do exactly the same thing as
AssumptionCache is that a lot more transforms touch branches and branch
conditions than assumptions. AssumptionCache is an immutable analysis
and mostly gets away with this because only a handful of places have to
register additional assumptions (mostly as a result of cloning). This is
very much not the case for branches.

This change regresses compile-time by about ~0.2%. It also improves
stage2-O0-g builds by about ~0.2%, which indicates that this change results
in additional optimizations inside clang itself.

Fixes https://github.com/llvm/llvm-project/issues/74242.

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[InstCombine] Infer disjoint flag on Or instructions. (#72912)

The disjoint flag was recently added to IR in #72583

We already set it when we turn an add into an or. This patch sets it on Ors tha

[InstCombine] Infer disjoint flag on Or instructions. (#72912)

The disjoint flag was recently added to IR in #72583

We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.

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[InstCombine] Fix incorrect nneg inference on shift amount

Whether this is valid depends on the bit widths of the involved
integers.

Fixes https://github.com/llvm/llvm-project/issues/72927.

[InstCombine] Add tests for incorrect shift nneg inference (NFC)

The second test is a miscompile.

[InstCombine] Infer shift flags with unknown shamt (#72535)

Alive2: https://alive2.llvm.org/ce/z/82Wr3q

Related patch:
https://github.com/llvm/llvm-project/commit/2dd52b4527667837cc525aa48435ab5

[InstCombine] Infer shift flags with unknown shamt (#72535)

Alive2: https://alive2.llvm.org/ce/z/82Wr3q

Related patch:
https://github.com/llvm/llvm-project/commit/2dd52b4527667837cc525aa48435ab5cbfa30a0b

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[InstCombine] Infer nsw flag for `(X <<nuw C1) >>u C --> X << (C1 - C)` (#72407)

Alive2: https://alive2.llvm.org/ce/z/nnHAPy
This missed optimization is discovered with the help of
https://github.

[InstCombine] Infer nsw flag for `(X <<nuw C1) >>u C --> X << (C1 - C)` (#72407)

Alive2: https://alive2.llvm.org/ce/z/nnHAPy
This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.

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[InstCombine] Infer zext nneg flag (#71534)

Use KnownBits to infer the nneg flag on zext instructions.

Currently we only set nneg when converting sext -> zext, but don't set
it when we have a ze

[InstCombine] Infer zext nneg flag (#71534)

Use KnownBits to infer the nneg flag on zext instructions.

Currently we only set nneg when converting sext -> zext, but don't set
it when we have a zext in the first place. If we want to use it in
optimizations, we should make sure the flag inference is consistent.

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[InstCombine] Drop exact flag instead of increasing demanded bits (#70311)

Demanded bit simplification for lshr/ashr will currently demand the low
bits if the exact flag is set. This is because the

[InstCombine] Drop exact flag instead of increasing demanded bits (#70311)

Demanded bit simplification for lshr/ashr will currently demand the low
bits if the exact flag is set. This is because these bits must be zero
to satisfy the flag.

However, this means that our demanded bits simplification is worse for
lshr/ashr exact than it is for plain lshr/ashr, which is generally not
desirable.

Instead, drop the exact flag if a demanded bits simplification of the
operand succeeds, which may no longer satisfy the exact flag.

This matches what we do for the exact flag on udiv, as well as the
nuw/nsw flags on add/sub/mul.

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[InstCombine] Add additional demanded bits tests for shifts (NFC)

[PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP

This patch tries to canonicalise add + gep to gep + gep.

Co-authored-by: Paul Walker <paul.walker@arm.com>

Reviewed By: nikic

Differential Revisi

[PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP

This patch tries to canonicalise add + gep to gep + gep.

Co-authored-by: Paul Walker <paul.walker@arm.com>

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D155688

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