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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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38fffa63 |
| 06-Nov-2024 |
Paul Walker <paul.walker@arm.com> |
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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a1058776 |
| 21-Aug-2024 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be can
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be canonicalized away. This is
indeed very useful to e.g. know that constants are always on the right.
However, this is only useful if the canonicalization is actually
reliable. This is the case for constants, but not for arguments: Moving
these to the right makes it look like the "more complex" expression is
guaranteed to be on the left, but this is not actually the case in
practice. It fails as soon as you replace the argument with another
instruction.
The end result is that it looks like things correctly work in tests,
while they actually don't. We use the "thwart complexity-based
canonicalization" trick to handle this in tests, but it's often a
challenge for new contributors to get this right, and based on the
regressions this PR originally exposed, we clearly don't get this right
in many cases.
For this reason, I think that it's better to remove this complexity
canonicalization. It will make it much easier to write tests for
commuted cases and make sure that they are handled.
show more ...
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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76d3ab2c |
| 20-Jun-2024 |
Nikita Popov <npopov@redhat.com> |
[IR] Remove support for shl constant expressions (#96037)
Remove support for shl constant expressions, as part of:
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5 |
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d9a5aa8e |
| 17-Apr-2024 |
Nikita Popov <npopov@redhat.com> |
[PatternMatch] Do not accept undef elements in m_AllOnes() and friends (#88217)
Change all the cstval_pred_ty based PatternMatch helpers (things like
m_AllOnes and m_Zero) to only allow poison elem
[PatternMatch] Do not accept undef elements in m_AllOnes() and friends (#88217)
Change all the cstval_pred_ty based PatternMatch helpers (things like
m_AllOnes and m_Zero) to only allow poison elements inside vector
splats, not undef elements.
Historically, we used to represent non-demanded elements in vectors
using undef. Nowadays, we use poison instead. As such, I believe that
support for undef in vector splats is no longer useful.
At the same time, while poison splat elements are pretty much always
safe to ignore, this is not generally the case for undef elements. We
have existing miscompiles in our tests due to this (see the
masked-merge-*.ll tests changed here) and it's easy to miss such cases
in the future, now that we write tests using poison instead of undef
elements.
I think overall, keeping support for undef elements no longer makes
sense, and we should drop it. Once this is done consistently, I think we
may also consider allowing poison in m_APInt by default, as doing that
change is much less risky than doing the same with undef.
This change involves a substantial amount of test changes. For most
tests, I've just replaced undef with poison, as I don't think there is
value in retaining both. For some tests (where the distinction between
undef and poison is important), I've duplicated tests.
show more ...
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Revision tags: llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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96adf69b |
| 23-Jan-2024 |
AtariDreams <83477269+AtariDreams@users.noreply.github.com> |
[InstCombine] Remove one-use check if other logic operand is constant (#77973)
By using `match(W, m_ImmConstant())`, we do not need to worry about
one-time use anymore.
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Revision tags: llvmorg-17.0.6 |
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26ce3e42 |
| 17-Nov-2023 |
Yingwei Zheng <dtcxzyw2333@gmail.com> |
[InstCombine] Preserve NSW flags for `lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2)` (#72625)
Alive2: https://alive2.llvm.org/ce/z/TU_V9M
This missed optimization is discovered with the h
[InstCombine] Preserve NSW flags for `lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2)` (#72625)
Alive2: https://alive2.llvm.org/ce/z/TU_V9M
This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.
show more ...
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Revision tags: llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1 |
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c17ccced |
| 27-Jan-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
Recommit "Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))" 2nd Try
First time caused build failure: https://lab.llvm.org/buildbot/#/builders/183/builds/1044
Recommit "Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))" 2nd Try
First time caused build failure: https://lab.llvm.org/buildbot/#/builders/183/builds/10447 but after investigating it seems to be unrelated. The same test/build passed later with the original commit here: https://lab.llvm.org/buildbot/#/builders/183/builds/10448
This is just expanding the existing pattern that exists for AND/XOR/OR and gets a bit more parallelism in from the instruction sequence.
Alive2: Add - https://alive2.llvm.org/ce/z/dSmPkV Sub1 - https://alive2.llvm.org/ce/z/6rpi5V Sub2 - https://alive2.llvm.org/ce/z/UfYeUd
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D141875
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423bcf89 |
| 28-Jan-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
Revert "Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))"
This reverts commit edd80befeeb92000800ded2a6f3dcdfd672d95ea.
Caused test failures in Clangd: https://
Revert "Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))"
This reverts commit edd80befeeb92000800ded2a6f3dcdfd672d95ea.
Caused test failures in Clangd: https://lab.llvm.org/buildbot/#/builders/183/builds/10447 reverting while investigating.
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edd80bef |
| 27-Jan-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))
This is just expanding the existing pattern that exists for AND/XOR/OR and gets a bit more parallelism in from t
Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))
This is just expanding the existing pattern that exists for AND/XOR/OR and gets a bit more parallelism in from the instruction sequence.
Alive2: Add - https://alive2.llvm.org/ce/z/dSmPkV Sub1 - https://alive2.llvm.org/ce/z/6rpi5V Sub2 - https://alive2.llvm.org/ce/z/UfYeUd
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D141875
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8c884655 |
| 27-Jan-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
Add tests for reoredering (shift (add (shift x, C0), y), C1); NFC
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D141874
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Revision tags: llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2 |
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4ab40eca |
| 03-Oct-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test][InstCombine] Update some test cases to use opaque pointers
These tests cases were converted using the script at https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34
Differential Re
[test][InstCombine] Update some test cases to use opaque pointers
These tests cases were converted using the script at https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34
Differential Revision: https://reviews.llvm.org/D135094
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Revision tags: llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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1fae4b49 |
| 20-Apr-2022 |
chenglin.bi <chenglin.bi@cixcomputing.com> |
[InstCombine] Fold mul nuw+lshr to a single multiplication when the latter is a factor
if c is divisible by (1 << ShAmtC), we can fold this pattern: lshr (mul nuw x, c), ShAmtC -> mul nuw x, (c >> S
[InstCombine] Fold mul nuw+lshr to a single multiplication when the latter is a factor
if c is divisible by (1 << ShAmtC), we can fold this pattern: lshr (mul nuw x, c), ShAmtC -> mul nuw x, (c >> ShAmtC)
https://alive2.llvm.org/ce/z/ox4wAt
Fix https://github.com/llvm/llvm-project/issues/54824
Reviewed By: spatel, lebedev.ri, craig.topper
Differential Revision: https://reviews.llvm.org/D123453
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8242fc7f |
| 20-Apr-2022 |
chenglin.bi <chenglin.bi@cixcomputing.com> |
[InstCombine] add tests for mul+lshr; NFC
Baseline tests for D123453(issue #54824)
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Revision tags: llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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acdc419c |
| 04-Feb-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://r
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119081
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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9e796d5e |
| 09-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] foldShiftOfShiftedLogic - add support for nonuniform constant vectors
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2efcb643 |
| 09-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Add nonuniform/undef vector tests for shift(binop(shift(x,c1),y),c2) patterns
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Revision tags: llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1 |
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5d67d81f |
| 17-Nov-2019 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] prevent crashing/assert on shift constant expression (PR44028)
The binary operator cast implies an instruction, but the matcher for shift does not: https://bugs.llvm.org/show_bug.cgi?i
[InstCombine] prevent crashing/assert on shift constant expression (PR44028)
The binary operator cast implies an instruction, but the matcher for shift does not: https://bugs.llvm.org/show_bug.cgi?id=44028
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d9ccb636 |
| 07-Nov-2019 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] canonicalize shift+logic+shift to reduce dependency chain
shift (logic (shift X, C0), Y), C1 --> logic (shift X, C0+C1), (shift Y, C1)
This is an IR translation of an existing SDAG tr
[InstCombine] canonicalize shift+logic+shift to reduce dependency chain
shift (logic (shift X, C0), Y), C1 --> logic (shift X, C0+C1), (shift Y, C1)
This is an IR translation of an existing SDAG transform added here: rL370617
So we again have 9 possible patterns with a commuted IR variant of each pattern: https://rise4fun.com/Alive/VlI https://rise4fun.com/Alive/n1m https://rise4fun.com/Alive/1Vn
Part of the motivation is to allow easier recognition and subsequent canonicalization of bswap patterns as discussed in PR43146: https://bugs.llvm.org/show_bug.cgi?id=43146
We had to delay this transform because it used to allow the SLP vectorizer to create awful reductions out of simple load-combines. That problem was fixed with: rL375025 (we'll bring back load combining in IR someday...)
The backend is also better equipped to deal with these patterns now using hooks like TLI.getShiftAmountThreshold().
The only remaining potential controversy is that the -reassociate pass tends to reverse this kind of pattern (to help GVN?). But since -reassociate doesn't do anything with these specific patterns, there is no conflict currently.
Finally, there's a new pass proposal at D67383 for general tree-height-reduction reassociation, and it could use a cost model to decide how to optimally rearrange these kinds of ops for a target. That patch appears to be stalled.
Differential Revision: https://reviews.llvm.org/D69842
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3ce0c785 |
| 05-Nov-2019 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add tests for shift-logic-shift; NFC
This is based on existing CodeGen test files for x86 and AArch64. The corresponding potential transform is shown in: rL370617
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