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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5 |
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| #
a6fefc82 |
| 21-Nov-2024 |
Yingwei Zheng <dtcxzyw2333@gmail.com> |
[InstCombine] Convert logical and/or with `icmp samesign` into bitwise ops (#116983)
See the following case:
```
define i1 @test_logical_and_icmp_samesign(i8 %x) {
%cmp1 = icmp ne i8 %x, 9
%
[InstCombine] Convert logical and/or with `icmp samesign` into bitwise ops (#116983)
See the following case:
```
define i1 @test_logical_and_icmp_samesign(i8 %x) {
%cmp1 = icmp ne i8 %x, 9
%cmp2 = icmp samesign ult i8 %x, 11
%and = select i1 %cmp1, i1 %cmp2, i1 false
ret i1 %and
}
```
Currently we cannot convert this logical and into a bitwise and due to
the `samesign` flag. But if `%cmp2` evaluates to `poison`, we can infer
that `%cmp1` is either `poison` or `true` (`samesign` violation
indicates that X is negative). Therefore, `%and` still evaluates to
`poison`.
This patch converts a logical and into a bitwise and iff TV is poison
implies that Cond is either poison or true. Likewise, we convert a
logical or into a bitwise or iff FV is poison implies that Cond is
either poison or false.
Note:
1. This logic is implemented in InstCombine. Not sure whether it is
profitable to move it into ValueTracking and call `impliesPoison(TV/FV,
Sel)` instead.
2. We only handle the case that `ValAssumedPoison` is `icmp samesign
pred X, C1` and `V` is `icmp pred X, C2`. There are no suitable variants
for `isImpliedCondition` to pass the fact that X is [non-]negative.
Alive2: https://alive2.llvm.org/ce/z/eorFfa
Motivation: fix [a major
regression](https://github.com/dtcxzyw/llvm-opt-benchmark/pull/1724#discussion_r1849663863)
to unblock https://github.com/llvm/llvm-project/pull/112742.
show more ...
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Revision tags: llvmorg-19.1.4 |
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| #
38fffa63 |
| 06-Nov-2024 |
Paul Walker <paul.walker@arm.com> |
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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| #
a1058776 |
| 21-Aug-2024 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be can
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be canonicalized away. This is
indeed very useful to e.g. know that constants are always on the right.
However, this is only useful if the canonicalization is actually
reliable. This is the case for constants, but not for arguments: Moving
these to the right makes it look like the "more complex" expression is
guaranteed to be on the left, but this is not actually the case in
practice. It fails as soon as you replace the argument with another
instruction.
The end result is that it looks like things correctly work in tests,
while they actually don't. We use the "thwart complexity-based
canonicalization" trick to handle this in tests, but it's often a
challenge for new contributors to get this right, and based on the
regressions this PR originally exposed, we clearly don't get this right
in many cases.
For this reason, I think that it's better to remove this complexity
canonicalization. It will make it much easier to write tests for
commuted cases and make sure that they are handled.
show more ...
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4 |
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| #
b1094776 |
| 11-Apr-2024 |
Yingwei Zheng <dtcxzyw2333@gmail.com> |
[InstCombine] Infer nsw/nuw for trunc (#87910)
This patch adds support for inferring trunc's nsw/nuw flags.
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| #
313a33b9 |
| 10-Apr-2024 |
XChy <xxs_chy@outlook.com> |
[InstCombine] Reduce nested logical operator if poison is implied (#86823)
Fixes #76623
Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to
write a proof for such transform, may
[InstCombine] Reduce nested logical operator if poison is implied (#86823)
Fixes #76623
Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to
write a proof for such transform, maybe there are mistakes)
In most cases, `icmp(a, C1) && (other_cond && icmp(a, C2))` will be
reduced to `icmp(a, C1) & (other_cond && icmp(a, C2))`, since latter
icmp always implies the poison of the former. After reduction, it's
easier to simplify the icmp chain.
Similarly, this patch does the same thing for `(A && B) && C --> A && (B
& C)`. Maybe we could constraint such reduction only on icmps if there
is regression in benchmarks.
show more ...
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Revision tags: llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3 |
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| #
fd07b8f8 |
| 15-Feb-2024 |
Paul Walker <paul.walker@arm.com> |
[LLVM][tests/Transforms/InstCombine] Convert instances of ConstantExpr based splats to use splat().
This is mostly NFC but some output does change due to consistently inserting into poison rather th
[LLVM][tests/Transforms/InstCombine] Convert instances of ConstantExpr based splats to use splat().
This is mostly NFC but some output does change due to consistently inserting into poison rather than undef and using i64 as the index type for inserts.
show more ...
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Revision tags: llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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| #
5a667bee |
| 19-Jan-2024 |
Alexey Bataev <5361294+alexey-bataev@users.noreply.github.com> |
[InstCombine] Try to fold trunc(shuffle(zext)) to just a shuffle (#78636)
Tries to remove extra trunc/ext instruction for shufflevector instructions.
Differential Review: https://github.com/llvm/ll
[InstCombine] Try to fold trunc(shuffle(zext)) to just a shuffle (#78636)
Tries to remove extra trunc/ext instruction for shufflevector instructions.
Differential Review: https://github.com/llvm/llvm-project/pull/78636
show more ...
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| #
4482fd84 |
| 19-Jan-2024 |
Pranav Kant <prka@google.com> |
Revert "[InstCombine] Try to fold trunc(shuffle(zext)) to just a shuffle (#78636)"
This reverts commit 4d11f04b20f0bd7488e19e8f178ba028412fa519.
This breaks some programs as mentioned in #78636
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| #
4d11f04b |
| 19-Jan-2024 |
Alexey Bataev <5361294+alexey-bataev@users.noreply.github.com> |
[InstCombine] Try to fold trunc(shuffle(zext)) to just a shuffle (#78636)
Tries to remove extra trunc/ext instruction for shufflevector
instructions.
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| #
a5f34155 |
| 18-Dec-2023 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Replace non-demanded undef vector with poison
If an operand (esp to shufflevector or insertelement) is not demanded, canonicalize it from undef to poison.
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| #
5c3496ff |
| 05-Dec-2023 |
Craig Topper <craig.topper@sifive.com> |
[InstCombine] Check isGuaranteedNotToBeUndef in haveNoCommonBitsSetSpecialCases. (#74390)
It's not safe for InstCombine to add disjoint metadata when converting
Add to Or otherwise.
I've added n
[InstCombine] Check isGuaranteedNotToBeUndef in haveNoCommonBitsSetSpecialCases. (#74390)
It's not safe for InstCombine to add disjoint metadata when converting
Add to Or otherwise.
I've added noundef attribute to preserve existing test behavior.
show more ...
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| #
7ec4f609 |
| 02-Dec-2023 |
Craig Topper <craig.topper@sifive.com> |
[InstCombine] Infer disjoint flag on Or instructions. (#72912)
The disjoint flag was recently added to IR in #72583
We already set it when we turn an add into an or. This patch sets it on Ors tha
[InstCombine] Infer disjoint flag on Or instructions. (#72912)
The disjoint flag was recently added to IR in #72583
We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.
show more ...
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4 |
|
| #
15915fa1 |
| 02-Mar-2023 |
Paul Walker <paul.walker@arm.com> |
[InstCombine] Implement "A & (~A | B) --> A & B" like transforms for boolean based selects.
Alive2 links for "A & (~A | B) --> A & B": https://alive2.llvm.org/ce/z/oKiodu (scalar) https://alive2.llv
[InstCombine] Implement "A & (~A | B) --> A & B" like transforms for boolean based selects.
Alive2 links for "A & (~A | B) --> A & B": https://alive2.llvm.org/ce/z/oKiodu (scalar) https://alive2.llvm.org/ce/z/8yn8GL (vector)
Alive2 links for "A | (~A & B) --> A | B" https://alive2.llvm.org/ce/z/v5GEKu (scalar) https://alive2.llvm.org/ce/z/wvtJsj (vector)
NOTE: The commutative variants of these transforms, for example: "(~A | B) & A --> A & B" are already handled by simplifying the underlying selects to normal logical operations due to that combination having simpler poison semantics.
Differential Revision: https://reviews.llvm.org/D145157
show more ...
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| #
6a7d5d37 |
| 03-Mar-2023 |
Paul Walker <paul.walker@arm.com> |
Precommit tests for D145157.
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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
|
| #
87b2c760 |
| 05-Jan-2023 |
chenglin.bi <chenglin.bi@linaro.org> |
[Instcombine] fold logic ops to select
(C & X) | ~(C | Y) -> C ? X : ~Y
https://alive2.llvm.org/ce/z/4yLh_i
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D139080
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| #
50a1c9b1 |
| 04-Jan-2023 |
chenglin.bi <chenglin.bi@linaro.org> |
[Instcombine] Regenerate tests for logical-select; NFC
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| #
18cae673 |
| 05-Dec-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[Instcombine] Precommit tests for D139080; NFC Test pattern for (C & X) | ~(C | Y) -> C ? X : ~Y
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4 |
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| #
2e999b7d |
| 01-Nov-2022 |
Philip Reames <preames@rivosinc.com> |
Allow scalable vectors in ComputeNumSignBits and isKnownNonNull
This is a follow up to D136470 which extends the same scheme used there to ComputeNumSignBits and isKnownNonNull. As a reminder, for s
Allow scalable vectors in ComputeNumSignBits and isKnownNonNull
This is a follow up to D136470 which extends the same scheme used there to ComputeNumSignBits and isKnownNonNull. As a reminder, for scalable vectors we track a single bit which is implicitly broadcast to all lanes. We do not know how many lanes there are statically, and thus have to be conservative along paths which require exact sizes.
Differential Revision: https://reviews.llvm.org/D137046
show more ...
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Revision tags: llvmorg-15.0.3 |
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| #
d85505a9 |
| 13-Oct-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] fold logical and/or to xor
(A | B) & ~(A & B) --> A ^ B
https://alive2.llvm.org/ce/z/qpFMns
We already have the equivalent fold for real logic instructions, but this pattern may occu
[InstCombine] fold logical and/or to xor
(A | B) & ~(A & B) --> A ^ B
https://alive2.llvm.org/ce/z/qpFMns
We already have the equivalent fold for real logic instructions, but this pattern may occur with selects too.
This is part of solving issue #58313.
show more ...
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| #
b78306c9 |
| 13-Oct-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add tests for logical select xor folds; NFC
issue #58313
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Revision tags: working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4 |
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| #
bafab9c0 |
| 05-May-2022 |
Fraser Cormack <fraser@codeplay.com> |
[InstCombine] Fix scalable-vector bitwise select matching
D113035 enhanced the matching of bitwise selects from vector types. This change unfortunately introduced crashes as it tries to cast scalabl
[InstCombine] Fix scalable-vector bitwise select matching
D113035 enhanced the matching of bitwise selects from vector types. This change unfortunately introduced crashes as it tries to cast scalable vector types to integers.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D124997
show more ...
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| #
21c028ac |
| 05-May-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] fix typo in test name; NFC
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| #
7bad1d28 |
| 05-May-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add scalable vector test for logical select; NFC
D124997 shows that the code is not ready to handle scalable vectors, so add some more coverage for a potential crashing case.
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2 |
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| #
2c2568f3 |
| 14-Apr-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] canonicalize select with signbit test
This is part of solving issue #54750 - in that example we have both forms of the compare and do not recognize the equivalence.
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Revision tags: llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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| #
acdc419c |
| 04-Feb-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://r
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119081
show more ...
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