History log of /llvm-project/llvm/test/Transforms/InstCombine/div-shift.ll (Results 1 – 25 of 43)
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Revision tags: llvmorg-21-init, llvmorg-19.1.7
# 2d5f07c8 11-Jan-2025 Veera <32646674+veera-sivarajan@users.noreply.github.com>

[InstCombine] Fold `X udiv Y` to `X lshr cttz(Y)` if Y is a power of 2 (#121386)

Fixes #115767

This PR folds `X udiv Y` to `X lshr cttz(Y)` if Y is a power of two
since bitwise operations are fa

[InstCombine] Fold `X udiv Y` to `X lshr cttz(Y)` if Y is a power of 2 (#121386)

Fixes #115767

This PR folds `X udiv Y` to `X lshr cttz(Y)` if Y is a power of two
since bitwise operations are faster than division.

Proof: https://alive2.llvm.org/ce/z/qHmLta

show more ...


Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4
# 38fffa63 06-Nov-2024 Paul Walker <paul.walker@arm.com>

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)


Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5
# 44cdbef7 13-Nov-2023 Yingwei Zheng <dtcxzyw2333@gmail.com>

[InstCombine] Infer nneg flag from shift users (#71947)

This patch sets `nneg` flag when the zext is only used by a shift.

Alive2: https://alive2.llvm.org/ce/z/h3xKjP
Compile-time impact:
https

[InstCombine] Infer nneg flag from shift users (#71947)

This patch sets `nneg` flag when the zext is only used by a shift.

Alive2: https://alive2.llvm.org/ce/z/h3xKjP
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=bd611264993f64decbce178d460caf1d1cb05f59&to=26bc473b239010bb24ff1bc39d58b42ecbbc4730&stat=instructions:u

This is an alternative to #71906.

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Revision tags: llvmorg-17.0.4
# f2898def 17-Oct-2023 XChy <xxs_chy@outlook.com>

[InstCombine] Don't mix X << Y / Z << Y with X << Y / X << Z (#69302)

Fixes #69291.
This patch improve the logic handling different patterns to avoid mixing these
pattern.


Revision tags: llvmorg-17.0.3
# 0823cb79 15-Oct-2023 XChy <xxs_chy@outlook.com>

[InstCombine] Fold (X << Y) / (X << Z) -> 1 << Y >> Z (#68863)

Resolve #68857.
Alive2 proofs:
[Whole proofs](https://alive2.llvm.org/ce/z/A5b85F)


Revision tags: llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2
# bfe2f5d3 18-Apr-2023 Noah Goldstein <goldstein.w.n@gmail.com>

[InstCombine] Fix buggy `(mul X, Y)` -> `(shl X, Log2(Y))` transform PR62175

Bug was because we recognized patterns like `(shl 4, Z)` as a power of
2 we could take Log2 of (`2 + Z`), but doing `(shl

[InstCombine] Fix buggy `(mul X, Y)` -> `(shl X, Log2(Y))` transform PR62175

Bug was because we recognized patterns like `(shl 4, Z)` as a power of
2 we could take Log2 of (`2 + Z`), but doing `(shl X, (2 + Z))` can
cause a poison shift.
https://alive2.llvm.org/ce/z/yuJm_k

The fix is to verify that `Log2(Y)` will be a non-poisonous shift
amount. We can do this with:
`nsw` flag:
- https://alive2.llvm.org/ce/z/yyyJBr
- https://alive2.llvm.org/ce/z/YgubD_
`nuw` flag:
- https://alive2.llvm.org/ce/z/-4mpyV
- https://alive2.llvm.org/ce/z/a6ik6r
Prove `Y != 0`:
- https://alive2.llvm.org/ce/z/ced4su
- https://alive2.llvm.org/ce/z/X-JJHb

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D148609

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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3
# 86b4d864 08-Feb-2023 Sanjay Patel <spatel@rotateright.com>

[InstCombine] canonicalize cmp+select as umin/umax

(V == 0) ? 1 : V --> umax(V, 1)
(V == UMAX) ? UMAX-1 : V --> umin(V, UMAX-1)

https://alive2.llvm.org/ce/z/pfDBAf

This is one pair of the variants

[InstCombine] canonicalize cmp+select as umin/umax

(V == 0) ? 1 : V --> umax(V, 1)
(V == UMAX) ? UMAX-1 : V --> umin(V, UMAX-1)

https://alive2.llvm.org/ce/z/pfDBAf

This is one pair of the variants discussed in issue #60374.

Enhancements for the other end of the constant range and
signed variants are potential follow-ups, but that may
require more work because we canonicalize at least one
min/max like that to icmp+zext.

show more ...


Revision tags: llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7
# 1f84e72b 29-Dec-2022 Chenbing Zheng <Chenbing.Zheng@streamcomputing.com>

[InstCombine] Fold (X << Z) / (X * Y) -> (1 << Z) / Y

Alive2: https://alive2.llvm.org/ce/z/CBJLeP


# bff1f8c7 23-Dec-2022 Chenbing Zheng <Chenbing.Zheng@streamcomputing.com>

[InstCombine] complete (X << Z) / (Y << Z) --> X / Y

Add one more situations for this fold.
For unsigned div, 'nsw' on both shifts + 'nuw' on the dividend.

Alive2: https://alive2.llvm.org/ce/z/sELF

[InstCombine] complete (X << Z) / (Y << Z) --> X / Y

Add one more situations for this fold.
For unsigned div, 'nsw' on both shifts + 'nuw' on the dividend.

Alive2: https://alive2.llvm.org/ce/z/sELF76

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D139997

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# d4493dd1 15-Dec-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add nuw to any (1<<x)

https://alive2.llvm.org/ce/z/9EjDKE

This was mentioned as a missing fold in D139598.

It can unlock follow-on folds in some cases.
This verifies one of the chang

[InstCombine] add nuw to any (1<<x)

https://alive2.llvm.org/ce/z/9EjDKE

This was mentioned as a missing fold in D139598.

It can unlock follow-on folds in some cases.
This verifies one of the changed tests:
https://alive2.llvm.org/ce/z/B_btDM

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# 3552f0a9 09-Dec-2022 Chenbing Zheng <Chenbing.Zheng@streamcomputing.com>

[InstCombine] Add tests for udiv with shl-mul; NFC


# 463e9be1 07-Dec-2022 Chenbing Zheng <Chenbing.Zheng@streamcomputing.com>

[InstCombine] Add tests for (X << Z) / (X * Y) -> (1 << Z) / Y. nfc


Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3
# 23fa3031 12-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add test for udiv with shl divisor; NFC

This would solve an example from issue #58137 more
generally, but it may require adding a canonicalization
for shift + shift to shift + add.


# 7b9482df 12-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] fold sdiv with common shl amount in operands

(X << Z) / (Y << Z) --> X / Y

https://alive2.llvm.org/ce/z/CLKzqT

This requires a surprising "nuw" constraint because we have
to guard ag

[InstCombine] fold sdiv with common shl amount in operands

(X << Z) / (Y << Z) --> X / Y

https://alive2.llvm.org/ce/z/CLKzqT

This requires a surprising "nuw" constraint because we have
to guard against immediate UB via signed-div overflow with
-1 divisor.

This extends 008a89037a49ca0d9 and is another transform
derived from issue #58137.

show more ...


# 008a8903 12-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] fold udiv with common shl amount in operands

(X << Z) / (Y << Z) --> X / Y

https://alive2.llvm.org/ce/z/E5eaxU

This fixes the motivating example from issue #58137,
but it is not the

[InstCombine] fold udiv with common shl amount in operands

(X << Z) / (Y << Z) --> X / Y

https://alive2.llvm.org/ce/z/E5eaxU

This fixes the motivating example from issue #58137,
but it is not the most general transform. We should
probably also convert left-shift in the divisor to
right-shift in the dividend for that, but that exposes
another missed canonicalization for shifts and adds.

show more ...


# fe97f950 12-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] propagate "exact" through folds of div

These folds were added recently with:
6b869be8100d
8da2fa856f1b
...but they didn't account for the "exact" attribute,
and that can be safely prop

[InstCombine] propagate "exact" through folds of div

These folds were added recently with:
6b869be8100d
8da2fa856f1b
...but they didn't account for the "exact" attribute,
and that can be safely propagated:
https://alive2.llvm.org/ce/z/F_WhnR
https://alive2.llvm.org/ce/z/ft9Cgr

show more ...


# 2639caf5 12-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add "exact" to div tests to show missing propagation; NFC


# bc032c7f 11-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add tests for div with shl operands; NFC


# 9cff4711 10-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] fold udiv with common factor

((X *nuw Y) >> Z) / X --> Y >> Z

https://alive2.llvm.org/ce/z/x3kKnq

This is similar to 6b869be8100d / 8da2fa856f1b, but I have
not found a signed equiva

[InstCombine] fold udiv with common factor

((X *nuw Y) >> Z) / X --> Y >> Z

https://alive2.llvm.org/ce/z/x3kKnq

This is similar to 6b869be8100d / 8da2fa856f1b, but I have
not found a signed equivalent, so it's just an unsigned
match for now.

show more ...


# 6876004f 10-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add 'exact' to udiv test for more coverage; NFC


# 68f267d2 06-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add tests for udiv with common factor; NFC


# f53d60e1 06-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add tests for udiv with shift-left divisor; NFC

issue #58137


# 8da2fa85 06-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] fold sdiv with hidden common factor

(X * Y) s/ (X << Z) --> Y s/ (1 << Z)

https://alive2.llvm.org/ce/z/yRSddG

issue #58137


# 6b869be8 06-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] fold udiv with hidden common factor

(X * Y) u/ (X << Z) --> Y u>> Z

https://alive2.llvm.org/ce/z/4G9D_W


# 34cca2bd 06-Oct-2022 Sanjay Patel <spatel@rotateright.com>

[InstCombine] add tests for div with common factor; NFC


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