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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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38fffa63 |
| 06-Nov-2024 |
Paul Walker <paul.walker@arm.com> |
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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a1058776 |
| 21-Aug-2024 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be can
[InstCombine] Remove some of the complexity-based canonicalization (#91185)
The idea behind this canonicalization is that it allows us to handle less
patterns, because we know that some will be canonicalized away. This is
indeed very useful to e.g. know that constants are always on the right.
However, this is only useful if the canonicalization is actually
reliable. This is the case for constants, but not for arguments: Moving
these to the right makes it look like the "more complex" expression is
guaranteed to be on the left, but this is not actually the case in
practice. It fails as soon as you replace the argument with another
instruction.
The end result is that it looks like things correctly work in tests,
while they actually don't. We use the "thwart complexity-based
canonicalization" trick to handle this in tests, but it's often a
challenge for new contributors to get this right, and based on the
regressions this PR originally exposed, we clearly don't get this right
in many cases.
For this reason, I think that it's better to remove this complexity
canonicalization. It will make it much easier to write tests for
commuted cases and make sure that they are handled.
show more ...
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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| #
3d795bdd |
| 11-Jan-2024 |
Yingwei Zheng <dtcxzyw2333@gmail.com> |
[InstCombine] Handle a bitreverse idiom which ends with a bswap (#77677)
This patch handles the following `bitreverse` idiom, which is found in
https://github.com/abseil/abseil-cpp/blob/8bd6445acc4
[InstCombine] Handle a bitreverse idiom which ends with a bswap (#77677)
This patch handles the following `bitreverse` idiom, which is found in
https://github.com/abseil/abseil-cpp/blob/8bd6445acc4bd0d123da2a44448b7218dfc70939/absl/crc/internal/crc.cc#L75-L80:
```
uint32_t ReverseBits(uint32_t bits) {
bits = (bits & 0xaaaaaaaau) >> 1 | (bits & 0x55555555u) << 1;
bits = (bits & 0xccccccccu) >> 2 | (bits & 0x33333333u) << 2;
bits = (bits & 0xf0f0f0f0u) >> 4 | (bits & 0x0f0f0f0fu) << 4;
return absl::gbswap_32(bits);
}
```
Alive2: https://alive2.llvm.org/ce/z/ZYXNmj
show more ...
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a5f34155 |
| 18-Dec-2023 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Replace non-demanded undef vector with poison
If an operand (esp to shufflevector or insertelement) is not demanded, canonicalize it from undef to poison.
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7ec4f609 |
| 02-Dec-2023 |
Craig Topper <craig.topper@sifive.com> |
[InstCombine] Infer disjoint flag on Or instructions. (#72912)
The disjoint flag was recently added to IR in #72583
We already set it when we turn an add into an or. This patch sets it on Ors tha
[InstCombine] Infer disjoint flag on Or instructions. (#72912)
The disjoint flag was recently added to IR in #72583
We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.
show more ...
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5 |
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68c5d46b |
| 25-May-2023 |
Austin Chang <austin880625@gmail.com> |
[InstCombine] Improve bitreverse optimization
This patch utilizes the helper function implemented in D149699 and thus folds the following cases:
``` bitreverse(logic_op(x, bitreverse(y))) -> logic_
[InstCombine] Improve bitreverse optimization
This patch utilizes the helper function implemented in D149699 and thus folds the following cases:
``` bitreverse(logic_op(x, bitreverse(y))) -> logic_op(bitreverse(x), y) bitreverse(logic_op(bitreverse(x), y)) -> logic_op(x, bitreverse(y)) bitreverse(logic_op(bitreverse(x), bitreverse(y))) -> logic_op(x, y) in multiuse case ```
Reviewed By: goldstein.w.n, RKSimon
Differential Revision: https://reviews.llvm.org/D151246
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1d1f7eee |
| 25-May-2023 |
Austin Chang <austin880625@gmail.com> |
[InstCombine] Add regression test cases for bitreverse optimization; NFC
Fold the following case on IR InstCombine pass. This patch includes the new test cases for this optimization
``` bitreverse(
[InstCombine] Add regression test cases for bitreverse optimization; NFC
Fold the following case on IR InstCombine pass. This patch includes the new test cases for this optimization
``` bitreverse(logic_op(x, bitreverse(y))) -> logic_op(bitreverse(x), y) bitreverse(logic_op(bitreverse(x), y)) -> logic_op(x, bitreverse(y)) bitreverse(logic_op(bitreverse(x), bitreverse(y))) -> logic_op(x, y) with multi-use ```
Reviewed By: goldstein.w.n
Differential Revision: https://reviews.llvm.org/D151245
show more ...
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Revision tags: llvmorg-16.0.4, llvmorg-16.0.3 |
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8b56da5e |
| 26-Apr-2023 |
ManuelJBrito <manuel.brito@tecnico.ulisboa.pt> |
[IR] Change shufflevector undef mask to poison
With this patch an undefined mask in a shufflevector will be printed as poison. This change is done to support the new shufflevector semantics for unde
[IR] Change shufflevector undef mask to poison
With this patch an undefined mask in a shufflevector will be printed as poison. This change is done to support the new shufflevector semantics for undefined mask elements.
Differential Revision: https://reviews.llvm.org/D149210
show more ...
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Revision tags: llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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0eedc9e5 |
| 09-Jan-2023 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] bitrev (zext i1 X) --> select X, SMinC, 0
https://alive2.llvm.org/ce/z/ZXCtgi
This breaks the infinite combine loop for issue #59897, but we may still need more changes to avoid those
[InstCombine] bitrev (zext i1 X) --> select X, SMinC, 0
https://alive2.llvm.org/ce/z/ZXCtgi
This breaks the infinite combine loop for issue #59897, but we may still need more changes to avoid those loops.
show more ...
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b1e69476 |
| 09-Jan-2023 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add tests for bitreverse of i1; NFC
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2 |
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4ab40eca |
| 03-Oct-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test][InstCombine] Update some test cases to use opaque pointers
These tests cases were converted using the script at https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34
Differential Re
[test][InstCombine] Update some test cases to use opaque pointers
These tests cases were converted using the script at https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34
Differential Revision: https://reviews.llvm.org/D135094
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Revision tags: llvmorg-15.0.1, llvmorg-15.0.0 |
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4db9edfd |
| 02-Sep-2022 |
Chenbing Zheng <Chenbing.Zheng@streamcomputing.com> |
[NFC] fix typo
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Revision tags: llvmorg-15.0.0-rc3 |
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adf4519c |
| 25-Aug-2022 |
Chenbing Zheng <Chenbing.Zheng@streamcomputing.com> |
[InstCombine] recognize bitreverse disguised as shufflevector
This patch complete TODO left in D66965, and achieve related pattern for bitreverse.
Reviewed By: RKSimon
Differential Revision: https
[InstCombine] recognize bitreverse disguised as shufflevector
This patch complete TODO left in D66965, and achieve related pattern for bitreverse.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D132431
show more ...
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6b3cbf60 |
| 23-Aug-2022 |
Chenbing Zheng <Chenbing.Zheng@streamcomputing.com> |
[InstCombine] add tests for shuf bitcast. nfc
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Revision tags: llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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acdc419c |
| 04-Feb-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://r
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119081
show more ...
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1 |
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401d6685 |
| 15-May-2021 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] InstCombinerImpl::visitOr - enable bitreverse matching
Currently we only match bswap intrinsics from or(shl(),lshr()) style patterns when we could often match bitreverse intrinsics alm
[InstCombine] InstCombinerImpl::visitOr - enable bitreverse matching
Currently we only match bswap intrinsics from or(shl(),lshr()) style patterns when we could often match bitreverse intrinsics almost as cheaply.
Differential Revision: https://reviews.llvm.org/D90170
show more ...
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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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a6ad077f |
| 23-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Add i8 bitreverse by multiplication test patterns
Pulled from bit twiddling hacks webpage
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61d1847b |
| 23-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Add 8/16/32/64 bitreverse test coverage
Use typical codegen for the traditional pairwise lgN bitreverse algorithm
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9e7667e2 |
| 23-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Add initial bitreverse test coverage
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