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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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f4b925ee |
| 30-Dec-2022 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
IROutliner: Convert tests to opaque pointers
Some of these show improvements. outlining-bitcasts.ll might not be
relevant anymore (or should be rewritten to test some other type of
non-pointer bitca
IROutliner: Convert tests to opaque pointers
Some of these show improvements. outlining-bitcasts.ll might not be
relevant anymore (or should be rewritten to test some other type of
non-pointer bitcast).
show more ...
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9dd9575c |
| 07-Dec-2022 |
Roman Lebedev <lebedev.ri@gmail.com> |
[NFC] Port all IROutliner tests to `-passes=` syntax
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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0c4bbd29 |
| 09-Mar-2022 |
Andrew Litteken <andrew.litteken@gmail.com> |
[IRSim] Make sure the first instruction of a block doesn't get missed if it is the first valid instruction in Module.
If an instruction is first legal instruction in the module, and is the only lega
[IRSim] Make sure the first instruction of a block doesn't get missed if it is the first valid instruction in Module.
If an instruction is first legal instruction in the module, and is the only legal instruction in its basic block, it will be ignored by the outliner due to a length check inherited from the older version of the outliner that was restricted to outlining within a single basic block. This removes that check, and updates any tests that broke because of it.
Reviewer: paquette
Differential Revision: https://reviews.llvm.org/D120786
show more ...
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Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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e8f4e41b |
| 02-Jan-2022 |
Andrew Litteken <andrew.litteken@gmail.com> |
[IRSim][IROutliner] Add support for outlining PHINodes with the rest of the region.
We use the same similarity scheme we used for branch instructions for phi nodes, and allow them to be outlined. Th
[IRSim][IROutliner] Add support for outlining PHINodes with the rest of the region.
We use the same similarity scheme we used for branch instructions for phi nodes, and allow them to be outlined. There is not a lot of special handling needed for these phi nodes when outlining, as they simply act as outputs. The code extractor does not currently allow for non entry blocks within the extracted region to have predecessors, so there are not conflicts to handle with respect to predecessors no longer contained in the function.
Recommit of 515eec3553b02533e9a88ee84bc245d5415163da
Reviewers: paquette
Differential Revision: https://reviews.llvm.org/D106997
show more ...
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515eec35 |
| 02-Jan-2022 |
Andrew Litteken <andrew.litteken@gmail.com> |
[IRSim][IROutliner] Add support for outlining PHINodes with the rest of the region.
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