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# 5a139141 14-Jan-2015 Jyoti Allur <jyoti.allur@samsung.com>

Correct POP handling for v7m

llvm-svn: 225972
# 0b5a8520 18-Dec-2014 Saleem Abdulrasool <compnerd@compnerd.org>

ARM: fix an off-by-one in the register list access

Fix an off-by-one access introduced in 224502 for push.w and pop.w with single
register operands. Add test cases for both scenarios.

Thanks to As

ARM: fix an off-by-one in the register list access

Fix an off-by-one access introduced in 224502 for push.w and pop.w with single
register operands. Add test cases for both scenarios.

Thanks to Asiri Rathnayake for pointing out the failure!

llvm-svn: 224521

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Revision tags: llvmorg-3.5.1, llvmorg-3.5.1-rc2
# 3a23917d 18-Dec-2014 Saleem Abdulrasool <compnerd@compnerd.org>

ARM: improve instruction validation for thumb mode

The ARM Architecture Reference Manual states the following:
LDM{,IA,DB}:
The SP cannot be in the list.
The PC can be in the list.
If

ARM: improve instruction validation for thumb mode

The ARM Architecture Reference Manual states the following:
LDM{,IA,DB}:
The SP cannot be in the list.
The PC can be in the list.
If the PC is in the list:
• the LR must not be in the list
• the instruction must be either outside any IT block, or the last
instruction in an IT block.
POP:
The PC can be in the list.
If the PC is in the list:
• the LR must not be in the list
• the instruction must be either outside any IT block, or the last
instruction in an IT block.
PUSH:
The SP and PC can be in the list in ARM instructions, but not in Thumb
instructions.
STM:{,IA,DB}:
The SP and PC can be in the list in ARM instructions, but not in Thumb
instructions.

llvm-svn: 224502

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