|
Revision tags: llvmorg-21-init, llvmorg-19.1.7 |
|
| #
eb812d28 |
| 19-Dec-2024 |
Feng Zou <feng.zou@intel.com> |
[X86] Put R20/R21/R28/R29 later in GR64 list (#120510)
Because these registers require an extra byte to encode in certain
memory form. Putting them later in the list will reduce code size when
EGP
[X86] Put R20/R21/R28/R29 later in GR64 list (#120510)
Because these registers require an extra byte to encode in certain
memory form. Putting them later in the list will reduce code size when
EGPR is enabled. And align the same order in GR8, GR16 and GR32 lists.
Example:
movq (%r20), %r11 # encoding: [0xd5,0x1c,0x8b,0x1c,0x24]
movq (%r22), %r11 # encoding: [0xd5,0x1c,0x8b,0x1e]
show more ...
|
|
Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3 |
|
| #
f3018879 |
| 06-Aug-2024 |
Freddy Ye <freddy.ye@intel.com> |
[X86][RA] Add two address hints for compressible NDD instructions. (#98603)
To address @topperc 's comment at
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/5?u=
[X86][RA] Add two address hints for compressible NDD instructions. (#98603)
To address @topperc 's comment at
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/5?u=kanrobert
show more ...
|
|
Revision tags: llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1 |
|
| #
821dee98 |
| 26-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Add NDD entries for isAssociativeAndCommutative
|
| #
d119ecb9 |
| 24-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][NFC] Pre-commit test for RA hints for APX NDD instructions
|
|
Revision tags: llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5 |
|
| #
c9017bc7 |
| 09-Nov-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Support EGPR (R16-R31) for APX (#70958)
1. Map R16-R31 to DWARF registers 130-145.
2. Make R16-R31 caller-saved registers.
3. Make R16-31 allocatable only when feature EGPR is supported
4.
[X86] Support EGPR (R16-R31) for APX (#70958)
1. Map R16-R31 to DWARF registers 130-145.
2. Make R16-R31 caller-saved registers.
3. Make R16-31 allocatable only when feature EGPR is supported
4. Make R16-31 availabe for instructions in legacy maps 0/1 and EVEX
space, except XSAVE*/XRSTOR
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Explanations for some seemingly unrelated changes:
inline-asm-registers.mir, statepoint-invoke-ra-enter-at-end.mir:
The immediate (TargetInstrInfo.cpp:1612) used for the regdef/reguse is
the encoding for the register
class in the enum generated by tablegen. This encoding will change
any time a new register class is added. Since the number is part
of the input, this means it can become stale.
seh-directive-errors.s:
R16-R31 makes ".seh_pushreg 17" legal
musttail-varargs.ll:
It seems some LLVM passes use the number of registers rather the number
of allocatable registers as heuristic.
This PR is to reland #67702 after #70222 in order to reduce some
compile-time regression when EGPR is not used.
show more ...
|
|
Revision tags: llvmorg-17.0.4, llvmorg-17.0.3 |
|
| #
feea5db0 |
| 10-Oct-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Support EGPR (R16-R31) for APX (#67702)
1. Map R16-R31 to DWARF registers 130-145.
2. Make R16-R31 caller-saved registers.
3. Make R16-31 allocatable only when feature EGPR is supported
4.
[X86] Support EGPR (R16-R31) for APX (#67702)
1. Map R16-R31 to DWARF registers 130-145.
2. Make R16-R31 caller-saved registers.
3. Make R16-31 allocatable only when feature EGPR is supported
4. Make R16-31 availabe for instructions in legacy maps 0/1 and EVEX
space, except XSAVE*/XRSTOR
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Explanations for some seemingly unrelated changes:
inline-asm-registers.mir, statepoint-invoke-ra-enter-at-end.mir:
The immediate (TargetInstrInfo.cpp:1612) used for the regdef/reguse is
the encoding for the register
class in the enum generated by tablegen. This encoding will change
any time a new register class is added. Since the number is part
of the input, this means it can become stale.
seh-directive-errors.s:
R16-R31 makes ".seh_pushreg 17" legal
musttail-varargs.ll:
It seems some LLVM passes use the number of registers rather the number
of allocatable registers as heuristic.
show more ...
|