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20683de7 |
| 26-Jun-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Not promote some binary ops from i16 to i32 if we have NDD variant
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7 |
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a9e8a3a1 |
| 29-May-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Extend X86CompressEVEX for NF transform
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Revision tags: llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2 |
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| #
7b766a6f |
| 17-Mar-2024 |
XinWang10 <108658776+XinWang10@users.noreply.github.com> |
[X86] Support APX CMOV/CFCMOV instructions (#82592)
This patch support ND CMOV instructions and CFCMOV instructions.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-sup
[X86] Support APX CMOV/CFCMOV instructions (#82592)
This patch support ND CMOV instructions and CFCMOV instructions.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
show more ...
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Revision tags: llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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| #
9095eec0 |
| 12-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support EVEX compression: NDD to nonNDD (#77731)
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| #
1fe7bdb8 |
| 11-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/763
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/76319
https://github.com/llvm/llvm-project/pull/76721
https://github.com/llvm/llvm-project/pull/76919
show more ...
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