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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7 |
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a9e8a3a1 |
| 29-May-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Extend X86CompressEVEX for NF transform
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Revision tags: llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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1fe7bdb8 |
| 11-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/763
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/76319
https://github.com/llvm/llvm-project/pull/76721
https://github.com/llvm/llvm-project/pull/76919
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