| #
20683de7 |
| 26-Jun-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Not promote some binary ops from i16 to i32 if we have NDD variant
|
| #
b6c9dcc9 |
| 20-Jun-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Not emit mr_ND if rr_ND is commutable
This gives us more chance to compress instruction in X86CompressEVEX.cpp
b/c mr_ND is not a candidate of instructions to be compressed while
rm_N
[X86][CodeGen] Not emit mr_ND if rr_ND is commutable
This gives us more chance to compress instruction in X86CompressEVEX.cpp
b/c mr_ND is not a candidate of instructions to be compressed while
rm_ND is.
show more ...
|
|
Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2 |
|
| #
5910e34a |
| 30-Jan-2024 |
XinWang10 <108658776+XinWang10@users.noreply.github.com> |
[X86][MC] Support encoding optimization & assembler relaxation about immediate operands for APX instructions (#78545)
Encoding optimization:
```
mi/mi32 -> mi8
ri/ri32 -> ri8
```
if the immedi
[X86][MC] Support encoding optimization & assembler relaxation about immediate operands for APX instructions (#78545)
Encoding optimization:
```
mi/mi32 -> mi8
ri/ri32 -> ri8
```
if the immediate operand is 8-bit wide.
Assembler relaxation:
```
mi8 -> mi/mi32
ri8 -> ri/ri32
```
If the immediate operand is a symbol expression and it's value is
unknown.
show more ...
|
|
Revision tags: llvmorg-18.1.0-rc1 |
|
| #
f7b61f81 |
| 24-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Transform NDD SUB to CMP if dest reg is dead (#79135)
|
|
Revision tags: llvmorg-19-init |
|
| #
f6617091 |
| 18-Jan-2024 |
XinWang10 <108658776+XinWang10@users.noreply.github.com> |
[X86][test] Add --show-mc-encoding for lowering tests of NDD arithmetic instructions (#78406)
#77564 added lowering tests for NDD arithmetic instructions.
It would be great to add `--show-mc-encodi
[X86][test] Add --show-mc-encoding for lowering tests of NDD arithmetic instructions (#78406)
#77564 added lowering tests for NDD arithmetic instructions.
It would be great to add `--show-mc-encoding` to check the NDD variant
is selected first.
show more ...
|
| #
9095eec0 |
| 12-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support EVEX compression: NDD to nonNDD (#77731)
|
| #
1fe7bdb8 |
| 11-Jan-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/763
[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564)
We supported encoding/decoding for these instructions in
https://github.com/llvm/llvm-project/pull/76319
https://github.com/llvm/llvm-project/pull/76721
https://github.com/llvm/llvm-project/pull/76919
show more ...
|