[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)

If c1 is a mask with c3 leading zeros and c3 is larger than c2.

Fixes regression reported in #101751.

[SelectionDAG] Allow FREEZE to be hoisted before integer SETCC. (#84241)

Teach canCreateUndefOrPoison that ISD::SETCC with integer operands can
never create undef/poison. FP SETCC is more complicat

[SelectionDAG] Allow FREEZE to be hoisted before integer SETCC. (#84241)

Teach canCreateUndefOrPoison that ISD::SETCC with integer operands can
never create undef/poison. FP SETCC is more complicated and will be
handled in a future patch.

Teach isGuaranteedNotToBeUndefOrPoison that ISD::CONDCODE is not
poison/undef. Its a special constant only used by setcc/select_cc like
nodes. This is needed since the hoisting will only hoist if exactly one
operand might be poison. setcc has 3 operand including the condition
code.

Recovers some regression from #84232.

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[RISCV] Insert a freeze before converting select to AND/OR. (#84232)

Select blocks poison, but AND/OR do not. We need to insert a freeze
to block poison propagation.

This creates suboptimal code

[RISCV] Insert a freeze before converting select to AND/OR. (#84232)

Select blocks poison, but AND/OR do not. We need to insert a freeze
to block poison propagation.

This creates suboptimal codegen which I will try to fix with other
patches. I'm prioritizing the correctness fix since we have 2 bug reports.

Fixes #84200 and #84350

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[RISCV] Enable the TypePromotion pass from AArch64/ARM.

This pass looks for unsigned icmps that have illegal types and tries
to widen the use/def graph to improve the placement of the zero
extends t

[RISCV] Enable the TypePromotion pass from AArch64/ARM.

This pass looks for unsigned icmps that have illegal types and tries
to widen the use/def graph to improve the placement of the zero
extends that type legalization would need to insert.

I've explicitly disabled it for i32 by adding a check for
isSExtCheaperThanZExt to the pass.

The generated code isn't perfect, but my data shows a net
dynamic instruction count improvement on spec2017 for both base and
Zba+Zbb+Zbs.

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[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ on

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ only due to the use of addi on rv32 vs addiw on rv64 when the
high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate
restriction on the compressed variants because we're not directly
forming the compressed variants. If we happen to get a zero immediate
for the ADDI, then either a later optimization will strip the useless
instruction or the encoder is responsible for not compressing the
instruction.

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[RISCV] Enable signed truncation check transforms for i8

This patch enables signed truncation check transforms for i8 on rv32 when XVT is i64 and Zbb is enabled.

It is a small improvement of D14997

[RISCV] Enable signed truncation check transforms for i8

This patch enables signed truncation check transforms for i8 on rv32 when XVT is i64 and Zbb is enabled.

It is a small improvement of D149977.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150177

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[RISCV] Implement shouldTransformSignedTruncationCheck.

This helps avoid constant materialization for the patterns
InstCombine emits for something like INT_MIN <= X && x <= INT_MAX.

See top of chan

[RISCV] Implement shouldTransformSignedTruncationCheck.

This helps avoid constant materialization for the patterns
InstCombine emits for something like INT_MIN <= X && x <= INT_MAX.

See top of changed test files for more detailed explanation.

I've enabled this for i16 when Zbb is enabled. sext.b did not seem
to be a benefit due to the constants folding into addi/sltiu.

This an alternative to https://reviews.llvm.org/D149814

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D149977

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[RISCV] Copy lack-of-signed-truncation-check.ll and signed-truncation-check.ll from AArch6/X86. NFC

This is a more exhaustive set of tests for the same issue D149814
is trying to solve.