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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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9122c523 |
| 15-Nov-2024 |
Pengcheng Wang <wangpengcheng.pp@bytedance.com> |
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional schedu
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional scheduling and tracking register
pressure.
Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.
show more ...
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2 |
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b6ea46fe |
| 07-Apr-2023 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.
Reviewed By: craig.topp
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D147538
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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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a63b7247 |
| 30-Dec-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./
isel is now capable of turning the SUB into XOR for shift amounts.
Though it uses NOT instead of XOR with ShiftSize-1.
B
[RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./
isel is now capable of turning the SUB into XOR for shift amounts.
Though it uses NOT instead of XOR with ShiftSize-1.
By using SUB during lowering we enable more DAG combines with
other arithmetic on the shift amount.
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| #
7cd72585 |
| 30-Dec-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X).
If the shift amount is (sub C, X) where C is -1 modulo the size of
the shift, we can replace the sub with a NOT.
We could als
[RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X).
If the shift amount is (sub C, X) where C is -1 modulo the size of
the shift, we can replace the sub with a NOT.
We could also use XORI X, size-1, but NOT would work better with
c.not from the future Zce extension.
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