[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/produc

[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700

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[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

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[RISCV] Convert some tests to opaque pointers (NFC)

[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.

This information is not preserved in MIR today. So this patch adds
information to RISCVMachineFunctionInfo when

[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.

This information is not preserved in MIR today. So this patch adds
information to RISCVMachineFunctionInfo when the vreg is created for
the argument.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D134621

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[RISCV] Remove support for the unratified Zbt extension.

This extension does not appear to be on its way to ratification.

Out of the unratified bitmanip extensions, this one had the
largest impact

[RISCV] Remove support for the unratified Zbt extension.

This extension does not appear to be on its way to ratification.

Out of the unratified bitmanip extensions, this one had the
largest impact on the compiler.

Posting this patch to start a discussion about whether we should
remove these extensions. We'll talk more at the RISC-V sync meeting this
Thursday.

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D133834

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[RISCV] Move xori creation for scalar setccs to lowering.

This patch enables expansion or custom lowering for some integer
condition codes so that any xori that is needed is created before
the last

[RISCV] Move xori creation for scalar setccs to lowering.

This patch enables expansion or custom lowering for some integer
condition codes so that any xori that is needed is created before
the last DAG combine to enable optimization.

I've seen cases where we end up with
(or (xori (setcc), 1), (xori (setcc), 1)) which we would ideally
convert to (xori (and (setcc), (setcc)), 1). This patch doesn't
accomplish that yet, but it should allow us to add DAG
combines as follow ups. Example https://godbolt.org/z/Y4qnvsq1b

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D131729

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[RISCV] Add more test cases for select with (setge X, C) condition.

InstCombine and SelectionDAG will tend to canonicalize these conditions
to (setgt X, C-1). C-1 might be more costly to materialize

[RISCV] Add more test cases for select with (setge X, C) condition.

InstCombine and SelectionDAG will tend to canonicalize these conditions
to (setgt X, C-1). C-1 might be more costly to materialize than C would
have been.

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[RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D122644

[RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)

setgt X, -1 is the canonical form of setge X, 0. We can swap the
select operands and use setlt X, X0 when selecting CMOV. This
avoid ma

[RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)

setgt X, -1 is the canonical form of setge X, 0. We can swap the
select operands and use setlt X, X0 when selecting CMOV. This
avoid materializing the -1 in a register.

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[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret`

[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret` usually. It is
a use of return address register. In some microarchitectures, there is
load-to-use data hazard. To avoid the load-to-use data hazard, we could
separate the load instruction from its use as far as possible. In this
patch, we reverse the order of restoring callee-saved registers to
increase the distance of `load ra` and `ret` in the epilog.

Differential Revision: https://reviews.llvm.org/D113967

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[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by r

[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
`llvm/utils/update_llc_test_checks.py`.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D112692

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[RISCV] Support RISCVISD::SELECT_CC in ComputeNumSignBitsForTargetNode.

[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.

This allows the use of BGE with X0 instead of puting -1/1 in a
register.

Reviewed By: jrtc27

Differential Revisio

[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.

This allows the use of BGE with X0 instead of puting -1/1 in a
register.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D98542

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[RISCV] Add test cases for failure to optimize select_cc with X < 1 or X > -1. NFC

We can use BGE with X0 to implement these, but we currently put
1 or -1 into a register.

Recommit "[RISCV] Legalize select when Zbt extension available"

This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with
the polarity of some of the pattern corrected.

Original commit message:

Recommit "[RISCV] Legalize select when Zbt extension available"

This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with
the polarity of some of the pattern corrected.

Original commit message:
The custom expansion of select operations in the RISC-V backend
interferes with the matching of cmov instructions. Legalizing
select when the Zbt extension is available solves that problem.

Reviewed By: luismarques, craig.topper

Differential Revision: https://reviews.llvm.org/D93767

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[RISCV][NFC] Increase test coverage of Zbt extension

Add Zbt (ternary) extension code generation to the select lowering
tests since it can have a significant impact on how select is
lowered.

While

[RISCV][NFC] Increase test coverage of Zbt extension

Add Zbt (ternary) extension code generation to the select lowering
tests since it can have a significant impact on how select is
lowered.

While we are here make the neg-abs commands more consistent with
the other tests.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94798

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[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llv

[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llvm-svn: 361493

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[RISCV] Implement frame pointer elimination

llvm-svn: 322839

[RISCV] Implement branch analysis

This is a prerequisite for the branch relaxation pass, and allows a number of
optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work.

Different

[RISCV] Implement branch analysis

This is a prerequisite for the branch relaxation pass, and allows a number of
optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work.

Differential Revision: https://reviews.llvm.org/D40808

llvm-svn: 322222

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[RISCV] Enable emission of alias instructions by default

This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC te

[RISCV] Enable emission of alias instructions by default

This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.

llvm-svn: 320797

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[RISCV] Implement prolog and epilog insertion

As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot o

[RISCV] Implement prolog and epilog insertion

As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot of the
RISC-V tests.

Differential Revision: https://reviews.llvm.org/D39849

llvm-svn: 320357

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[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR n

[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665

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[RISCV] Implement lowering of ISD::SELECT

Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
ex

[RISCV] Implement lowering of ISD::SELECT

Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch
will be created in the case where an ISD::SELECT condition value is created by
an ISD::SETCC node, which operates on XLen types. Other datatypes such as
floating point don't have conditional branch instructions, and lowering
ISD::SELECT allows more flexibility for handling these cases.

Differential Revision: https://reviews.llvm.org/D29937

llvm-svn: 318735

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