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Revision tags: llvmorg-21-init, llvmorg-19.1.7 |
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814902a0 |
| 27-Dec-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Fix XTheadba patterns broken since cfc574a6cd13d2d0b77110b579c5cfcec744129f.
Adding an OperandTransform to CSImm12MulBy4 and CSImm12MulBy8 for
Zba broke these patterns. They should have been
[RISCV] Fix XTheadba patterns broken since cfc574a6cd13d2d0b77110b579c5cfcec744129f.
Adding an OperandTransform to CSImm12MulBy4 and CSImm12MulBy8 for
Zba broke these patterns. They should have been changed in the same,
but we lacked sufficient testing.
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| #
cd3c1658 |
| 27-Dec-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add more tests to rv*xtheadba.ll. NFC
XTheadba has similarities with Zba and shares some of the same
codegen code and has similar isel patterns. This patch makes the
testing more similar.
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Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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| #
3e55ac94 |
| 20-Jun-2024 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
This is a three instruction expansion, and does not depend on zba, so
most of the test changes are in base RV32/64I configurations.
With zba, th
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
This is a three instruction expansion, and does not depend on zba, so
most of the test changes are in base RV32/64I configurations.
With zba, this gets immediates such as 14, 28, 30, 56, 60, 62.. which
aren't covered by our other expansions.
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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| #
9e1ad3cf |
| 31-Dec-2023 |
Jim Lin <jim@andestech.com> |
[RISCV] Remove blank lines at the end of testcases. NFC.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2 |
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| #
e25b30d9 |
| 08-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba. It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBa is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143029
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