[RISCV] Remove experimental for zihintntl

Since zihintntl is ratified now, we could remove the experimental prefix and change its version to 1.0.

Reviewed By: asb

Differential Revision: https://re

[RISCV] Remove experimental for zihintntl

Since zihintntl is ratified now, we could remove the experimental prefix and change its version to 1.0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D151547

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[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

This commit implements the two NTLH intrinsic functions.

```
type __riscv_ntl_load (type *ptr, int domain);
void __risc

[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

This commit implements the two NTLH intrinsic functions.

```
type __riscv_ntl_load (type *ptr, int domain);
void __riscv_ntl_store (type *ptr, type val, int domain);

```

```
enum {
__RISCV_NTLH_INNERMOST_PRIVATE = 2,
__RISCV_NTLH_ALL_PRIVATE,
__RISCV_NTLH_INNERMOST_SHARED,
__RISCV_NTLH_ALL
};
```

We encode the non-temporal domain into MachineMemOperand flags.

1. Create the RISC-V built-in function with custom semantic checking.
2. Assume the domain argument is a compile time constant,
and make it as LLVM IR metadata (nontemp_node).
3. Encode domain value as two bits MachineMemOperand TargetMMOflag.
4. According to MachineMemOperand TargetMMOflag, select corrsponding ntlh instruction.

Currently, it supports scalar type and fixed-length vector type.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143364

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[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand

Differential Revision: https://reviews.llvm.org/D143361