Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

This reverts commit 2501ae58e3bb9a70d279a56d7b3a0ed70a8a852c.

Reverted due to various buildbot failures.

[CodeGen] Really renumber slot indexes before register allocation (#67038)

PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries

[CodeGen] Really renumber slot indexes before register allocation (#67038)

PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries for instructions which
had been erased. Fix this to make the register allocator's live range
length heuristics even less dependent on the history of how instructions
have been added to and removed from SlotIndexes's maps.

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[SelectionDAG] Improve expansion of wide min/max

The current implementation tries to handle the high and low halves
separately, but that's less efficient in most cases; use a wide SETCC
instead.

Di

[SelectionDAG] Improve expansion of wide min/max

The current implementation tries to handle the high and low halves
separately, but that's less efficient in most cases; use a wide SETCC
instead.

Differential Revision: https://reviews.llvm.org/D151358

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[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.

We can compute a simpler expression for Lo for these cases. This
is an al

[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.

We can compute a simpler expression for Lo for these cases. This
is an alternative for the test cases in D151180 that works for
more targets.

This is similar to some of the special cases we have for expanding
setcc operands.

Differential Revision: https://reviews.llvm.org/D151182

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[RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1)

This patch reduces the number of unpredictable branches.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D146117

[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect

Same with (select C, X, -1), (select C, 0, X), and (select C, X, 0).

There's a DAGCombine after we turn the select into select_cc, but

[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect

Same with (select C, X, -1), (select C, 0, X), and (select C, X, 0).

There's a DAGCombine after we turn the select into select_cc, but
that may introduce a setcc that didn't previously exist. We could
add more DAGCombines to remove the extra setcc, but this seemed lower
effort.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135833

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[RISCV] Use branchless form for selects with -1 in either arm

We can lower these as an or with the negative of the condition value. This appears to result in significantly less branch-y code on mult

[RISCV] Use branchless form for selects with -1 in either arm

We can lower these as an or with the negative of the condition value. This appears to result in significantly less branch-y code on multiple common idioms (as seen in tests).

Differential Revision: https://reviews.llvm.org/D135316

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[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.

Similar to D132211, we can optimize x <s -1 ? x : -1 -> x <s 0 ? x : -1

Also improve the unsigned case from D132211 to use x != 0 which
wi

[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.

Similar to D132211, we can optimize x <s -1 ? x : -1 -> x <s 0 ? x : -1

Also improve the unsigned case from D132211 to use x != 0 which
will give a bnez instruction which might be compressible.

Differential Revision: https://reviews.llvm.org/D132252

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[SelectionDAG] Further improve computeKnownBits for (smax X, C) where C is non-negative.

Move the code that was added for D126896 after the normal recursive calls
to computeKnownBits. This allows us

[SelectionDAG] Further improve computeKnownBits for (smax X, C) where C is non-negative.

Move the code that was added for D126896 after the normal recursive calls
to computeKnownBits. This allows us to calculate trailing zeros.
Previously we would break out of the switch before the recursive calls.

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[DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.

If C is non-negative, the result of the smax must also be
non-negative, so all sign bits of the result are 0.

[DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.

If C is non-negative, the result of the smax must also be
non-negative, so all sign bits of the result are 0.

This allows DAGCombiner to remove a zext_inreg in the modified test.
This zext_inreg started as a sext that became zext before type
legalization then was promoted to a zext_inreg.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126896

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[RISCV] Add test case showing unnecessary extend after i32 smax on rv64. NFC

One of the operands of the smax is a positive value so computeKnownBits
determines the result of the smax must always be

[RISCV] Add test case showing unnecessary extend after i32 smax on rv64. NFC

One of the operands of the smax is a positive value so computeKnownBits
determines the result of the smax must always be positive. This allows
DAG combiner to convert the sign extend to zero extend before type
legalization.

After type legalization the smax is promoted to i64 by sign extending
its inputs and the zero extend becomes an AND instruction. We are unable
to remove the AND at this point and it becomes a pair of shifts or a
zext.w.

The result of smax has as many sign bits as the minimum of its inputs.
Had we kept the sign extend instead of turning it into a zero extend
it would be removed by DAG combiner after type legalization.

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[DAGCombiner] Fold (sext/zext undef) -> 0 and aext(undef) -> undef.

Differential Revision: https://reviews.llvm.org/D124988

[DAGCombiner] Fold (max/min X, X) -> X.

Differential Revision: https://reviews.llvm.org/D124951

[RISCV] Add integer min/max intrinsic tests. NFC

Add basic tests and some tests for same operands and all undef
operands inspired by PR55271.

i32 is umin/umax is using signext to match RISC-V ABI.

[RISCV] Add integer min/max intrinsic tests. NFC

Add basic tests and some tests for same operands and all undef
operands inspired by PR55271.

i32 is umin/umax is using signext to match RISC-V ABI. i8/i16 are
using signext/zeroext to match the operation.

Differential Revision: https://reviews.llvm.org/D124948

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