[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Model integer min max instructions from Zbb execute in late-B ALU

We don't model the early vs late ALU so we just need to remove usage of
SiFivePipeA for these instructions.

[RISCV] Enable PostRAScheduler for SiFive7 (#83166)

Based on numbers collected in our downstream toolchain.

[RISCV] Move compressible registers to the beginning of the FP allocation order.

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register

[RISCV] Move compressible registers to the beginning of the FP allocation order.

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register to be f8-f15.

This patch changes the FP allocation order to prioritize f10-f15 first.
These are also the FP argument registers. So I allocated them in reverse
order starting at f15 to avoid taking the first argument registers.
This appears to match gcc allocation order.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146488

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[RISCV] Add MULW to RISCVStripWSuffix.

This converts MULW to MUL if the upper bits aren't used.
This will give more opportunities to use c.mul with Zcb.

[MachineCombiner] Support local strategy for traces

For in-order cores MachineCombiner makes better decisions when the critical path
is calculated only for the current basic block and does not take

[MachineCombiner] Support local strategy for traces

For in-order cores MachineCombiner makes better decisions when the critical path
is calculated only for the current basic block and does not take into account
other blocks from the trace.

This patch adds a virtual method to TargetInstrInfo to allow each target decide
which strategy to use.

Depends on D140541

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D140542

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[RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative

Follow-up patch of D140530.

We can add FMIN, FMAX to isAssociativeAndCommutative to
increase instruction-level parallelism b

[RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative

Follow-up patch of D140530.

We can add FMIN, FMAX to isAssociativeAndCommutative to
increase instruction-level parallelism by the existing MachineCombiner
pass.

Differential Revision: https://reviews.llvm.org/D140602

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[RISCV] Add integer scalar instructions to isAssociativeAndCommutative

Inspired by D138107.

We can add ADD, AND, OR, XOR, MUL, MIN[U]/MAX[U] to isAssociativeAndCommutative
to increase instruction-l

[RISCV] Add integer scalar instructions to isAssociativeAndCommutative

Inspired by D138107.

We can add ADD, AND, OR, XOR, MUL, MIN[U]/MAX[U] to isAssociativeAndCommutative
to increase instruction-level parallelism by the existing MachineCombiner pass.

Differential Revision: https://reviews.llvm.org/D140530

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[MachineCombiner][RISCV] Support inverse instructions reassociation

This patch adds reassociation of FADD/FSUB instruction pairs.

Differential Revision: https://reviews.llvm.org/D138660

[MachineCombiner] Extend reassociation logic to handle inverse instructions

Machine combiner supports generic reassociation only of associative and
commutative instructions, for example (A + X) + Y

[MachineCombiner] Extend reassociation logic to handle inverse instructions

Machine combiner supports generic reassociation only of associative and
commutative instructions, for example (A + X) + Y => (X + Y) + A. However, we
can extend this generic support to handle patterns like
(X + A) - Y => (X - Y) + A), where `-` is the inverse of `+`.
This patch adds interface functions to process reassociation patterns of
associative/commutative instructions and their inverse variants with minimal
changes in backends.

Differential Revision: https://reviews.llvm.org/D136754

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[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns

This patch adds tranformation of fmul+fadd/fsub chains to fused multiply
instructions:
* fmul+fadd->fmadd
* fmul+fsub->fmsub

[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns

This patch adds tranformation of fmul+fadd/fsub chains to fused multiply
instructions:
* fmul+fadd->fmadd
* fmul+fsub->fmsub/fnmsub

We also will try to combine these instructions if the fmul has more than one use
and cannot be deleted. However, removing the dependence between fmul and fadd can
still be profitable, and we rely on machine combiner approximations of scheduling.

Differential Revision: https://reviews.llvm.org/D136764

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[MachineCombiner][RISCV] Precommit tests for D136764

[MachineCombiner][RISCV] Relax optimization level requirement

Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Origin

[MachineCombiner][RISCV] Relax optimization level requirement

Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.

Differential Revision: https://reviews.llvm.org/D136339

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[RISCV] Remove -enable-unsafe-fp-math from machine combiner tests. NFC

The optimization is using fast math flags on the instructions instead.

[MachineCombiner][RISCV] Enable MachineCombiner for RISCV

Initial implementation to match basic FP reassociation patterns.

Differential Revision: https://reviews.llvm.org/D135264

Revert "[MachineCombiner][RISCV] Enable MachineCombiner for RISCV"

This reverts commit 3112cf3b00fe45a0911ec0c2e6706ef1f8a9b972.
Test breakage: https://lab.llvm.org/buildbot/#/builders/16/builds/366

Revert "[MachineCombiner][RISCV] Enable MachineCombiner for RISCV"

This reverts commit 3112cf3b00fe45a0911ec0c2e6706ef1f8a9b972.
Test breakage: https://lab.llvm.org/buildbot/#/builders/16/builds/36631

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[MachineCombiner][RISCV] Enable MachineCombiner for RISCV

Initial implementation to match basic FP reassociation patterns.

Differential Revision: https://reviews.llvm.org/D135264

[MachineCombiner][RISCV] Precommit test for D135264