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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3 |
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| #
b6c79073 |
| 11-Oct-2022 |
Anton Sidorenko <anton.sidorenko@syntacore.com> |
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
This patch adds tranformation of fmul+fadd/fsub chains to fused multiply
instructions:
* fmul+fadd->fmadd
* fmul+fsub->fmsub
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
This patch adds tranformation of fmul+fadd/fsub chains to fused multiply
instructions:
* fmul+fadd->fmadd
* fmul+fsub->fmsub/fnmsub
We also will try to combine these instructions if the fmul has more than one use
and cannot be deleted. However, removing the dependence between fmul and fadd can
still be profitable, and we rely on machine combiner approximations of scheduling.
Differential Revision: https://reviews.llvm.org/D136764
show more ...
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| #
374d0765 |
| 12-Oct-2022 |
Anton Sidorenko <anton.sidorenko@syntacore.com> |
[MachineCombiner][RISCV] Precommit tests for D136764
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| #
14a5b9cd |
| 19-Oct-2022 |
Anton Sidorenko <anton.sidorenko@syntacore.com> |
[MachineCombiner][RISCV] Relax optimization level requirement
Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.
Origin
[MachineCombiner][RISCV] Relax optimization level requirement
Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.
Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.
Differential Revision: https://reviews.llvm.org/D136339
show more ...
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| #
061566d9 |
| 19-Oct-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Remove -enable-unsafe-fp-math from machine combiner tests. NFC
The optimization is using fast math flags on the instructions instead.
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| #
1978b4d9 |
| 17-Oct-2022 |
Anton Sidorenko <anton.sidorenko@syntacore.com> |
[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
Initial implementation to match basic FP reassociation patterns.
Differential Revision: https://reviews.llvm.org/D135264
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| #
3112cf3b |
| 17-Oct-2022 |
Anton Sidorenko <anton.sidorenko@syntacore.com> |
[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
Initial implementation to match basic FP reassociation patterns.
Differential Revision: https://reviews.llvm.org/D135264
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