[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret

After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret

This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.

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[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.

Instead of using getReservedRegs, just check the subtarget reserved
list. getReservedR

[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.

Instead of using getReservedRegs, just check the subtarget reserved
list. getReservedRegs considers the frame pointer to be reserved when
it is being used, but we do need to save/restore it so it should be
counted as a callee saved register. AArch64 hardcodes their callee
saved size, but the comment mentions the Frame Pointer being counted.

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[RISCV] Don't add getFrameIndexInstrOffset in RISCVRegisterInfo::needsFrameBaseReg.

It's already added in isFrameOffsetLegal so adding it in needsFrameBaseReg
causes it to be double counted.

[RISCV] Improve testing of loads with offset in local-stack-slot-allocation.ll. NFC

The test we had didn't match it's description.

Now we have one test with a large offset that requires a virtual b

[RISCV] Improve testing of loads with offset in local-stack-slot-allocation.ll. NFC

The test we had didn't match it's description.

Now we have one test with a large offset that requires a virtual base register
and a test with a smaller offset that should not.

There is currently a bug that causes the offset to double counted
leading to the small case also using a virtual base register.

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[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

When AMOs are used to implement parallel reduction operations, typically the return value would be

[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVDeadRegisterDefinitions`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158759

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[RISCV] Use LBU for extloadi8.

The Zcb extension has c.lbu, but not c.lb. This patch makes us
prefer LBU over LB if we have a choice which will enable more
compression opportunities.

Reviewed By: a

[RISCV] Use LBU for extloadi8.

The Zcb extension has c.lbu, but not c.lb. This patch makes us
prefer LBU over LB if we have a choice which will enable more
compression opportunities.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146270

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Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"

This includes a fix for the tramp3d failure from the llvm-testsuite
that caused the last revert. Hopefully the others failures wer

Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"

This includes a fix for the tramp3d failure from the llvm-testsuite
that caused the last revert. Hopefully the others failures were the
same issue.

Original commit message:
For RISC-V, load/store(exclude vector load/store) instructions only has a 12 bit immediate operand. If the offset is out-of-range, it must make use of a temp register to make up this offset. If between these offsets, they have a small(IsInt<12>) relative offset, LocalStackSlotAllocation pass can find a value as frame base register's value, and replace the origin offset with this register's value plus the relative offset.

Co-authored-by: luxufan <luxufan@iscas.ac.cn>
Co-authored-by: Craig Topper <craig.topper@sifive.com>

Differential Revision: https://reviews.llvm.org/D98101

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Revert "[RISCV] Enable the LocalStackSlotAllocation pass support."

This reverts commit 180397cdded67a8fdf56f92a0b70d32f0dac8af6.

This seems to cause llvm-testsuite failures.

[RISCV] Enable the LocalStackSlotAllocation pass support.

Differential Revision: https://reviews.llvm.org/D98101

Co-authored-by: luxufan <luxufan@iscas.ac.cn>

[RISCV] Convert some tests to opaque pointers (NFC)

[RISCV] Fold low 12 bits into instruction during frame index elimination

Fold the low 12 bits of an immediate offset into the offset field of the using instruction. That using instruction will be a

[RISCV] Fold low 12 bits into instruction during frame index elimination

Fold the low 12 bits of an immediate offset into the offset field of the using instruction. That using instruction will be a load, store, or addi which performs an add of a signed 12-bit immediate as part of it's operation. Splitting out the low bits allows the high bits to be generated via a single LUI instead of needing an LUI/ADDI pair.

The codegen effect of this is mostly converting cases where "split addi" kicks in to using LUI + a folded offset. There are a couple of straight dynamic instruction count wins, and using a canonical LUI is probably better than a chain of SP adds if the dynamic instruction count is equal.

Differential Revision: https://reviews.llvm.org/D139037

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Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"

This reverts commit 82c820b95cf7ec284baf182cf838ca9e26758098.

This failed llvm-testsuite in our downstream and a similar issue
was

Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"

This reverts commit 82c820b95cf7ec284baf182cf838ca9e26758098.

This failed llvm-testsuite in our downstream and a similar issue
was reported by @rogfer01.

show more ...

[RISCV] Enable the LocalStackSlotAllocation pass support

For RISC-V, load/store(exclude vector load/store) instructions only
has a 12 bit immediate operand. If the offset is out-of-range, it
must ma

[RISCV] Enable the LocalStackSlotAllocation pass support

For RISC-V, load/store(exclude vector load/store) instructions only
has a 12 bit immediate operand. If the offset is out-of-range, it
must make use of a temp register to make up this offset. If between
these offsets, they have a small(IsInt<12>) relative offset,
LocalStackSlotAllocation pass can find a value as frame base register's
value, and replace the origin offset with this register's value plus
the relative offset.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98101

show more ...

[RISCV] Add a LocalStackSlotAllocation test

Differential Revision: https://reviews.llvm.org/D134884