[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret

After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret

This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.

show more ...

[RISCV] Convert some tests to opaque pointers (NFC)

[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)

This reuses the existing optimized implementation of adjustReg, and commons up code. This has the effect of enabl

[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)

This reuses the existing optimized implementation of adjustReg, and commons up code. This has the effect of enabling two code changes for the new caller. First, we enable the "split andi" lowering (with no alignment requirement), and second we use a sub with smaller constant in register instead of a add with negative constant in register.

Differential Revision: https://reviews.llvm.org/D132839

show more ...

[RISCV] Merge addi into load/store as there is a ADD between them

This patch adds peephole optimizations for the following patterns:

(load (add base, (addi src, off1)), off2)
-> (load (add base,

[RISCV] Merge addi into load/store as there is a ADD between them

This patch adds peephole optimizations for the following patterns:

(load (add base, (addi src, off1)), off2)
-> (load (add base, src), off1+off2)
(store val, (add base, (addi src, off1)), off2)
-> (store val, (add base, src), off1+off2)

Differential Revision: https://reviews.llvm.org/D124231

show more ...

[RISCV] Fix incomplete asm statement parsing

For instructions without operands, the final `AsmToken::EndOfStatement`
wasn't being consumed. In the context of inline assembly, the resulting
empty sta

[RISCV] Fix incomplete asm statement parsing

For instructions without operands, the final `AsmToken::EndOfStatement`
wasn't being consumed. In the context of inline assembly, the resulting
empty statements would cause extraneous empty lines to be emitted. Fix
the issue by consuming the `EndOfStatement` token.

Differential Revision: https://reviews.llvm.org/D117565

show more ...

[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret`

[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret` usually. It is
a use of return address register. In some microarchitectures, there is
load-to-use data hazard. To avoid the load-to-use data hazard, we could
separate the load instruction from its use as far as possible. In this
patch, we reverse the order of restoring callee-saved registers to
increase the distance of `load ra` and `ret` in the epilog.

Differential Revision: https://reviews.llvm.org/D113967

show more ...

[RISCV] remove redundant instruction when eliminate frame index

The reason for generating mv a0, a0 instruction is when the stack object offset is large then int<12>. To deal this situation, in the

[RISCV] remove redundant instruction when eliminate frame index

The reason for generating mv a0, a0 instruction is when the stack object offset is large then int<12>. To deal this situation, in the elimintateFrameIndex function, it will
create a virtual register, which needs the register scavenger to scavenge it. If the machine instruction that contains the stack object and the opcode is ADDI(the addi
was generated by frameindexNode), and then this instruction's destination register was the same as the register that was generated by the register scavenger, then the
mv a0, a0 was generated. So to eliminnate this instruction, in the eliminateFrameIndex function, if the instrution opcode is ADDI, then the virtual register can't be created.

Differential Revision: https://reviews.llvm.org/D92479

show more ...

[RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and adde

[RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841

show more ...

[MC][RISCV] Set UseIntegratedAssembler to true

to align with most other targets. Also, -fintegrated-as is the default
for clang -target riscv*.

[RISCV] Fix wrong CFI directives

Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directive

[RISCV] Fix wrong CFI directives

Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directives. See the branch_and_tail_call test for an
example of the issue. Should fix the stack unwinding issues caused by
the incorrect directives.

Reviewers: asb, lenary, shiva0217
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69723

show more ...

Revert "[RISCV] Fix wrong CFI directives"

test/DebugInfo/RISCV/relax-debug-frame.ll wasn't properly updated.

[RISCV] Fix wrong CFI directives

Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directive

[RISCV] Fix wrong CFI directives

Summary: Removes CFI CFA directives that could incorrectly propagate
beyond the basic block they were inteded for. Specifically it removes
the epilogue CFI directives. See the branch_and_tail_call test for an
example of the issue. Should fix the stack unwinding issues caused by
the incorrect directives.

Reviewers: asb, lenary, shiva0217
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69723

show more ...

[RISCV] Fix CFA when doing split sp adjustment with fp

Summary: When using the split sp adjustment and using the frame-pointer
we were still emitting CFI CFA directives based on the sp value. The
fi

[RISCV] Fix CFA when doing split sp adjustment with fp

Summary: When using the split sp adjustment and using the frame-pointer
we were still emitting CFI CFA directives based on the sp value. The
final sp-based offset also didn't reflect the two-stage sp adjust. There
remain CFI issues that aren't related to the split sp adjustment, and
thus will be addressed in a separate patch.

Reviewers: asb, lenary, shiva0217
Reviewed By: lenary, shiva0217
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69385

show more ...

[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore

We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the follow

[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore

We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.

add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64

Differential Revision: https://reviews.llvm.org/D68011

llvm-svn: 373688

show more ...

[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated

[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.

llvm-svn: 356063

show more ...

Replace "no-frame-pointer-*" function attributes with "frame-pointer"

Part of the effort to refactoring frame pointer code generation. We used
to use two function attributes "no-frame-pointer-elim"

Replace "no-frame-pointer-*" function attributes with "frame-pointer"

Part of the effort to refactoring frame pointer code generation. We used
to use two function attributes "no-frame-pointer-elim" and
"no-frame-pointer-elim-non-leaf" to represent three kinds of frame
pointer usage: (all) frames use frame pointer, (non-leaf) frames use
frame pointer, (none) frame use frame pointer. This CL makes the idea
explicit by using only one enum function attribute "frame-pointer"

Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as
llc.

"no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still
supported for easy migration to "frame-pointer".

tests are mostly updated with

// replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’
grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g"

// replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’
grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g"

Patch by Yuanfang Chen (tabloid.adroit)!

Differential Revision: https://reviews.llvm.org/D56351

llvm-svn: 351049

show more ...

[RISCV] Implement frame pointer elimination

llvm-svn: 322839

[RISCV] Reserve an emergency spill slot for the register scavenger when necessary

Although the register scavenger can often find a spare register, an emergency
spill slot is needed to guarantee suc

[RISCV] Reserve an emergency spill slot for the register scavenger when necessary

Although the register scavenger can often find a spare register, an emergency
spill slot is needed to guarantee success. Reserve this slot in cases where
the function is known to have a large stack (meaning the scavenger may be
needed when forming stack addresses).

llvm-svn: 322269

show more ...

[RISCV] Support stack frames and offsets up to 32-bits

Differential Revision: https://reviews.llvm.org/D40807

llvm-svn: 322216