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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0 |
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1c874bbb |
| 03-Sep-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
Select only needs branches and moves so we don't need to promote it.
Promoting would canonicalize NaNs which select shouldn't do.
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Revision tags: llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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9e1ad3cf |
| 31-Dec-2023 |
Jim Lin <jim@andestech.com> |
[RISCV] Remove blank lines at the end of testcases. NFC.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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| #
12fee611 |
| 17-Jun-2023 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.llvm.org/ce/z/BZNEia
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152128
show more ...
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5 |
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| #
548fa1d3 |
| 31-May-2023 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT
Use sint_to_fp instead of select.
Reduce the number of branch instructions and
avoid generating TargetConstantPool for double.
(sel
[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT
Use sint_to_fp instead of select.
Reduce the number of branch instructions and
avoid generating TargetConstantPool for double.
(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
https://godbolt.org/z/n543Y9v3e
(select cc, 0.0, 1.0) -> (sint_to_fp (zext (xor cc, 1)))
https://alive2.llvm.org/ce/z/zngvSB
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D151719
show more ...
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Revision tags: llvmorg-16.0.4 |
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| #
773b0aaa |
| 12-May-2023 |
Qihan Cai <qcai8733@uni.sydney.edu.au> |
[RISCV][CodeGen] Support Zhinx and Zhinxmin
This patch was split from D122918.
Co-Author: @liaolucy @sunshaoce
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D149811
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Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
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| #
7b0c4184 |
| 28-Mar-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Move compressible registers to the beginning of the FP allocation order.
We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register
[RISCV] Move compressible registers to the beginning of the FP allocation order.
We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register to be f8-f15.
This patch changes the FP allocation order to prioritize f10-f15 first.
These are also the FP argument registers. So I allocated them in reverse
order starting at f15 to avoid taking the first argument registers.
This appears to match gcc allocation order.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146488
show more ...
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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| #
7b50c183 |
| 30-Nov-2022 |
Monk Chiang <monk.chiang@sifive.com> |
[RISCV] Codegen support for Zfhmin.
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also incl
[RISCV] Codegen support for Zfhmin.
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.
RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139391
show more ...
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3 |
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| #
39707c1a |
| 17-Aug-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
We fold integer setcc into SELECT_CC during DAG combine even if
the SELECT_CC has FP result type, but we had no test coverage.
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