[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to on

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to only spill 32 bits.

I've added CodeGenOnly instructions for load/store using GPRF32 as that gave better results than insert_subreg/extract_subreg.

Function arguments use this new GPRF32 register class for f32 arguments with Zfinx. Eliminating the need to use RISCVISD::FMV* nodes.

This is similar to #107446 which adds a 16 bit register class.

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[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)

[RISCV] Remove blank lines at the end of testcases. NFC.

[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC

fp-imm.ll and zfh-imm.ll test 0.0 and -0.0 while float/double/half-imm.ll
tested other non-zero constants. It seems like the

[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC

fp-imm.ll and zfh-imm.ll test 0.0 and -0.0 while float/double/half-imm.ll
tested other non-zero constants. It seems like they should all be
tested together.

There are slight coverage changes due to different command lines,
but I'm not sure its meaningful. For example, we now don't test
double 0.0 and -0.0 with only the F extension.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156929

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[RISCV][CodeGen] Support Zfinx codegen

This patch was split from D122918 . Co-Author: @liaolucy @realqhc

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D148874

[RISCV] Move compressible registers to the beginning of the FP allocation order.

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register

[RISCV] Move compressible registers to the beginning of the FP allocation order.

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register to be f8-f15.

This patch changes the FP allocation order to prioritize f10-f15 first.
These are also the FP argument registers. So I allocated them in reverse
order starting at f15 to avoid taking the first argument registers.
This appears to match gcc allocation order.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146488

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[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.

In addition, this commit does the following combine

vfm

[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.

In addition, this commit does the following combine

vfmv.v.f + fmv.[dhw].x -> vmv.v.x
vfmv.s.f + fmv.[dhw].x -> vmv.s.x
vfmerge.vfm + fmv.[dhw].x -> vmerge.vxm

Differential Revision: https://reviews.llvm.org/D142953

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[RISCV] Use check-prefixes to reduce check lines

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125083

[RISCV] Update some tests to use floating point ABI where it makes sense.

Trying to reduce the diffs from D118333 for cases where it makes
more sense to use an FP ABI.

Reviewed By: asb, kito-cheng

[RISCV] Update some tests to use floating point ABI where it makes sense.

Trying to reduce the diffs from D118333 for cases where it makes
more sense to use an FP ABI.

Reviewed By: asb, kito-cheng

Differential Revision: https://reviews.llvm.org/D120447

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[RISCV] Support Constant Pools in Load/Store Peephole

Summary:
RISC-V uses a post-select peephole pass to optimise
`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.
This

[RISCV] Support Constant Pools in Load/Store Peephole

Summary:
RISC-V uses a post-select peephole pass to optimise
`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.
This peephole wasn't firing for accesses to constant pools, which is how we
materialise most floating point constants.

This adds support for the constantpool case, which improves code generation for
lots of small FP loading examples. I have not added any tests because this
structure is well-covered by the `fp-imm.ll` testcases, as well as almost
all other uses of floating point constants in the RISC-V backend tests.

Reviewed By: luismarques, asb

Differential Revision: https://reviews.llvm.org/D79523

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Revert "[RISCV] Support Constant Pools in Load/Store Peephole"

This reverts commit fe69dfebcfa007e23bf528fff8b96ac63e593e34, due to
a slight change in the API.

[RISCV] Support Constant Pools in Load/Store Peephole

Summary:
RISC-V uses a post-select peephole pass to optimise
`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.
This

[RISCV] Support Constant Pools in Load/Store Peephole

Summary:
RISC-V uses a post-select peephole pass to optimise
`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.
This peephole wasn't firing for accesses to constant pools, which is how we
materialise most floating point constants.

This adds support for the constantpool case, which improves code generation for
lots of small FP loading examples. I have not added any tests because this
structure is well-covered by the `fp-imm.ll` testcases, as well as almost
all other uses of floating point constants in the RISC-V backend tests.

Reviewed By: luismarques, asb

Differential Revision: https://reviews.llvm.org/D79523

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[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revisio

[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106

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Revert Patch from Phabricator

This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)

llvm-svn: 372104

Patch from Phabricator

llvm-svn: 372092

[RISCV] Add RV64F codegen support

This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during l

[RISCV] Add RV64F codegen support

This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.

Differential Revision: https://reviews.llvm.org/D53235

llvm-svn: 352807

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[RISCV] Add codegen for RV32F floating point load/store

As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.

llvm-svn: 327979