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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
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576d81ba |
| 20-Mar-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
Previously we used memory like we do to move between GPRs and FPR64 with
the D extension on RV32.
We
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
Previously we used memory like we do to move between GPRs and FPR64 with
the D extension on RV32.
We can instead use REG_SEQUENCE/EXTRACT_SUBREG to inform register
allocation how to do the copy without memory.
show more ...
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Revision tags: llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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9e1ad3cf |
| 31-Dec-2023 |
Jim Lin <jim@andestech.com> |
[RISCV] Remove blank lines at the end of testcases. NFC.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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12fee611 |
| 17-Jun-2023 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.llvm.org/ce/z/BZNEia
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152128
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5 |
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548fa1d3 |
| 31-May-2023 |
LiaoChunyu <chunyu@iscas.ac.cn> |
[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT
Use sint_to_fp instead of select.
Reduce the number of branch instructions and
avoid generating TargetConstantPool for double.
(sel
[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT
Use sint_to_fp instead of select.
Reduce the number of branch instructions and
avoid generating TargetConstantPool for double.
(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
https://godbolt.org/z/n543Y9v3e
(select cc, 0.0, 1.0) -> (sint_to_fp (zext (xor cc, 1)))
https://alive2.llvm.org/ce/z/zngvSB
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D151719
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8b90f8e0 |
| 25-May-2023 |
Shao-Ce SUN <sunshaoce@iscas.ac.cn> |
[RISCV][CodeGen] Support Zdinx on RV32 codegen
This patch was split from D122918 .
Co-Author: @StephenFan @liaolucy @realqhc
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.
[RISCV][CodeGen] Support Zdinx on RV32 codegen
This patch was split from D122918 .
Co-Author: @StephenFan @liaolucy @realqhc
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D149743
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Revision tags: llvmorg-16.0.4 |
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2dc0fa05 |
| 03-May-2023 |
Shao-Ce SUN <sunshaoce@iscas.ac.cn> |
[RISCV][CodeGen] Support Zdinx on RV64 codegen
This patch was split from D122918 . Co-Author: @liaolucy @realqhc
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D149665
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Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3 |
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39707c1a |
| 17-Aug-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
We fold integer setcc into SELECT_CC during DAG combine even if
the SELECT_CC has FP result type, but we had no test coverage.
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