[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

Ventana doesn't have RV32 cores so the instructions aren't really
supported for RV32, but there's nothing specifically 64-bit about th

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

Ventana doesn't have RV32 cores so the instructions aren't really
supported for RV32, but there's nothing specifically 64-bit about them.

My goal here is to fix cannot select errors if XVentanaCondOps is
enabled on RV32. Alternatively, we could quality the lowering code to
also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing
the isel patterns seemed simpler.

Fixes #100855.

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[RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888)

There are no checks that the type is legal so we need to handle any
type.

[RISCV] Graduate Zicond to non-experimental (#79811)

The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tun

[RISCV] Graduate Zicond to non-experimental (#79811)

The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tuning that could be done about when to select Zicond or not, there
are no known correctness issues. Therefore, we should mark support as
non-experimental.

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[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

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[RISCV] Refine pattern (select_cc seteq (and x, C), 0, 0, A) with Zbs. (#73746)

PR #72978 disabled transformation (select_cc seteq (and x, C), 0, 0, A)
-> (and (sra(shl x)), A) for better Zicond co

[RISCV] Refine pattern (select_cc seteq (and x, C), 0, 0, A) with Zbs. (#73746)

PR #72978 disabled transformation (select_cc seteq (and x, C), 0, 0, A)
-> (and (sra(shl x)), A) for better Zicond codegen. It still enables the
combine when C is not fit into 12-bits. This patch disables the combine
when Zbs enabled.

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[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. (#73649)

Currently, llvm can transform (setcc ne (and x, c)) to (bexti x,
log2(c)) where c is power of 2.
This patch

[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. (#73649)

Currently, llvm can transform (setcc ne (and x, c)) to (bexti x,
log2(c)) where c is power of 2.
This patch transform (select (setcc ne (and x, c)), T, F) into (select
(setcc eq (and x, c)), F, T).
It is benefit to the case c is not fit to 12-bits.

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[TargetLowering][RISCV] Introduce shouldFoldSelectWithSingleBitTest and RISC-V implement. (#72978)

DAGCombiner folds (select_cc seteq (and x, y), 0, 0, A) to (and (sra
(shl x)) A) where y has a sin

[TargetLowering][RISCV] Introduce shouldFoldSelectWithSingleBitTest and RISC-V implement. (#72978)

DAGCombiner folds (select_cc seteq (and x, y), 0, 0, A) to (and (sra
(shl x)) A) where y has a single bit set. Previously, DAGCombiner relies
on `shouldAvoidTransformToShift` to decide when to do the combine, but
`shouldAvoidTransformToShift` is only about shift cost. This patch
introuduces a specific hook to decide when to do the combine and disable
the combine when Zicond enabled and AndMask <= 1024.

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[RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps.

[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.

This removes selectSETCC and adds isel patterns for seteq/setne
conditions.

This removes the duplication of selectSETCC be

[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.

This removes selectSETCC and adds isel patterns for seteq/setne
conditions.

This removes the duplication of selectSETCC between lowering and
isel. This also gets some cases in xaluo.ll that we missed previously.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D156250

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[RISCV] Add DAG combine to pull xor with 1 through select idiom that uses czero_eqz/nez.

If we are selecting between two setccs that need to be legalized
with xor, the select will be legalized first

[RISCV] Add DAG combine to pull xor with 1 through select idiom that uses czero_eqz/nez.

If we are selecting between two setccs that need to be legalized
with xor, the select will be legalized first. Detect this pattern
so we can pull the xor through to expose it to additional
optimizations.

We could generalize this to other operations, but those normally
get handled in DAG combine before select legalization.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156159

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[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.

If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 thr

[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.

If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 through the
select to enable more optimizations.

We could generalize this to other binary operators with identical
conditions, but those are usually caught before we legalize the select.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156144

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[RISCV] Add CZERO_EQZ/CZERO_NEZ to ComputeNumSignBitsForTargetNode.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D156082

[RISCV] Add test case for D156082 to condops.ll

This test is copied from select-cc.ll. It wasn't worth adding
Zicond RUN lines to that file.

Reviewed By: asb, wangpc

Differential Revision: https:/

[RISCV] Add test case for D156082 to condops.ll

This test is copied from select-cc.ll. It wasn't worth adding
Zicond RUN lines to that file.

Reviewed By: asb, wangpc

Differential Revision: https://reviews.llvm.org/D156083

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[RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y is 0 or 1.

This is an alternative to D155288 that can handle other sources of
xori like FP compares. Unfortunately, it

[RISCV] Add a DAG combine for (czero_eq X, (xor Y, 1)) -> (czero_ne X, Y) if Y is 0 or 1.

This is an alternative to D155288 that can handle other sources of
xori like FP compares. Unfortunately, it misses the i64 setge case
on RV32 in condops.ll.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155328

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[RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.

This makes Zicond and XVentanaCondOps use the same code path.
The instructions have identical semantics.

Reviewed By: wangpc

Differen

[RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.

This makes Zicond and XVentanaCondOps use the same code path.
The instructions have identical semantics.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155391

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[RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC

This is a case that D155288 won't get.

Reviewed By: asb

Differential Revision: https://reviews.llvm.or

[RISCV] Add FP compare test to condops.ll to show a missed opportunity to remove an xori. NFC

This is a case that D155288 won't get.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155327

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[RISCV][test] Add RV32I and RV64I RUN lines to condops.ll test

Some of these test cases will be changed by upcoming combines, even in
the non-zicond case.

[RISCV] Introduce RISCVISD::CZERO_{EQZ,NEZ} nodes produce them when zicond is present in lowerSELECT

This patch is a step towards altering how we handle the emission of
condops. Marking ISD::SELECT

[RISCV] Introduce RISCVISD::CZERO_{EQZ,NEZ} nodes produce them when zicond is present in lowerSELECT

This patch is a step towards altering how we handle the emission of
condops. Marking ISD::SELECT as legal is a major change in the codegen
path, and gives few options for maintaining the old codegen path when
it is believed to be better (e.g. a better branchless sequence is
possible using non-zicond instructions, or the branch-based sequence is
preferable).

This removes the existing SelectionDAG patterns and moves the logic into
lowerSELECT. Along some small codegen changes you'll note a few minor
regressions in the generated code quality - this are due to the fact
that by lowering the SELECT node early we miss out on combines that
would kick in later when setcc condcodes that aren't natively supported
have been expanded (thus exposing opportunities for optimisation by
performing logical negation and swapping truev/falsev). I've opted to
split out work that addresses these into follow-on patches (especially
as zicond is still 'experimental').

matchSetCC is a straight-forward translation from the version in
RISCVISelDAGToDAG. Ideally, in the future it can be converted to a
helper shared between both files.

Differential Revision: https://reviews.llvm.org/D155083

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[RISCV] Removed the requirement of XLenVT for performSELECTCombine.

Reviewed By: Craig Topper

Differential Revision: https://reviews.llvm.org/D153044

[RISCV] Add codegen for the experimental zicond extension

This directly matches the codegen for xventanacondops with vt.maskcn =>
czero.nez and vt.maskc => czero.eqz. An additional difference is tha

[RISCV] Add codegen for the experimental zicond extension

This directly matches the codegen for xventanacondops with vt.maskcn =>
czero.nez and vt.maskc => czero.eqz. An additional difference is that
zicond is available on RV32 in addition to RV64 (xventanacondops is RV64
only).

Differential Revision: https://reviews.llvm.org/D147147

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[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
in

[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681

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