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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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c532ba4e |
| 15-Dec-2023 |
Wang Yaduo <wangyaduo@linux.alibaba.com> |
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-he
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.
show more ...
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| #
fc3adf74 |
| 15-Dec-2023 |
Vitaly Buka <vitalybuka@google.com> |
Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (#75561)
Reverts llvm/llvm-project#74053
Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291
Co-aut
Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (#75561)
Reverts llvm/llvm-project#74053
Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291
Co-authored-by: Wang Yaduo <wangyaduo@linux.alibaba.com>
Issue #75563
show more ...
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| #
3dde0d02 |
| 15-Dec-2023 |
Wang Yaduo <wangyaduo@linux.alibaba.com> |
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-he
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.
show more ...
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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| #
6e4be7e1 |
| 27-Jun-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines.
Make Zcf/Zcd depend on Zca.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D153826
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