Revert "[LSR][TTI][RISCV] Disable terminator folding for RISC-V."

This reverts commit fdb87640ee2be63af9b0e0cd943cb13d79686a03, and thus
re-enables terminator folding for RISCV. The reported miscom

Revert "[LSR][TTI][RISCV] Disable terminator folding for RISC-V."

This reverts commit fdb87640ee2be63af9b0e0cd943cb13d79686a03, and thus
re-enables terminator folding for RISCV. The reported miscompile has
been fixed in f5dd70c58277d925710e5a7c25c86d7565cc3c6c.

show more ...

[LSR][TTI][RISCV] Disable terminator folding for RISC-V.

This is a partial revert of e947f953370abe8ffc8713b8f3250a3ec39599fe.

It caused a miscompile in downstream testing.

Spoke with Philip offli

[LSR][TTI][RISCV] Disable terminator folding for RISC-V.

This is a partial revert of e947f953370abe8ffc8713b8f3250a3ec39599fe.

It caused a miscompile in downstream testing.

Spoke with Philip offline. We believe the issue is that LSR needs to
make sure the Step of the other AddRec is non-zero. Reverting until
Philip is back from vacation.

show more ...

[LSR][TTI][RISCV] Enable terminator folding for RISC-V

If looking for a miscompile revert candidate, look here!

The transform being enabled prefers comparing to a loop invariant
exit value for a se

[LSR][TTI][RISCV] Enable terminator folding for RISC-V

If looking for a miscompile revert candidate, look here!

The transform being enabled prefers comparing to a loop invariant
exit value for a secondary IV over using an otherwise dead primary
IV. This increases register pressure (by requiring the exit value
to be live through the loop), but reduces the number of instructions
within the loop by one.

On RISC-V which has a large number of scalar registers, this is
generally a profitable transform. We loose the ability to use a beqz
on what is typically a count down IV, and pay the cost of computing
the exit value on the secondary IV in the loop preheader, but save
an add or sub in the loop body. For anything except an extremely
short running loop, or one with extreme register pressure, this is
profitable. On spec2017, we see a 0.42% geomean improvement in
dynamic icount, with no individual workload regressing by more than
0.25%.

Code size wise, we trade a (possibly compressible) beqz and a (possibly
compressible) addi for a uncompressible beq. We also add instructions
in the preheader. Net result is a slight regression overall, but
neutral or better inside the loop.

Previous versions of this transform had numerous cornercase correctness
bugs. All of them ones I can spot by inspection have been fixed, and I
have run this through all of spec2017, but there may be further issues
lurking. Adding uses to an IV is a fraught thing to do given poison
semantics, so this transform is somewhat inherently risky.

This patch is a reworked version of D134893 by @eop. That patch has
been abandoned since May, so I picked it up, reworked it a bit, and
am landing it.

show more ...

[RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare

Similar to ARM and SystemZ.

Related Patchs: D101778(preferZeroCompareBranch)
https://reviews.llvm.org/rG9a9421a46

[RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare

Similar to ARM and SystemZ.

Related Patchs: D101778(preferZeroCompareBranch)
https://reviews.llvm.org/rG9a9421a461166482465e786a46f8cced63cd2e9f ( == 0 to u< 1）

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D142071

show more ...

[LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half.

[LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half. Usually
we do (setult Lo, LHSLo). If RHSLo is 1 we can instead do (seteq Lo, 0).
This can reduce the live range of LHSLo.

show more ...

[RISCV] Add precommit tests for D142071;