[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

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[DAGCombine] Add DAG optimisation for BF16_TO_FP (#69426)

fold bf16_to_fp(op & 0xffff) -> bf16_to_fp(op)

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ on

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ only due to the use of addi on rv32 vs addiw on rv64 when the
high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate
restriction on the compressed variants because we're not directly
forming the compressed variants. If we happen to get a zero immediate
for the ADDI, then either a later optimization will strip the useless
instruction or the encoder is responsible for not compressing the
instruction.

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Recommit "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"

Without the changes from D153598.

Original commit message:

For the same reasons as D151284, this requires custom lo

Recommit "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"

Without the changes from D153598.

Original commit message:

For the same reasons as D151284, this requires custom lowering of the
truncate libcall on hard float ABIs (the normal libcall code path is
used on soft ABIs).

The extend operation is implemented by a shift just as in the standard
legalisation, but needs to be custom lowered because i32 isn't a legal
type on RV64.

This patch aims to make the minimal changes that result in correct
codegen for the bfloat.ll tests.

Differential Revision: https://reviews.llvm.org/D151663

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Revert "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"

This was committed with D153598 merged into it. Reverting to recommit as separate patches.

This reverts commit 690b1c8

Revert "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"

This was committed with D153598 merged into it. Reverting to recommit as separate patches.

This reverts commit 690b1c847f0b188202a86dc25a0a76fd8c4618f4.

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[RISCV] Implement support for bf16 truncate/extend on hard FP targets

For the same reasons as D151284, this requires custom lowering of the
truncate libcall on hard float ABIs (the normal libcall co

[RISCV] Implement support for bf16 truncate/extend on hard FP targets

For the same reasons as D151284, this requires custom lowering of the
truncate libcall on hard float ABIs (the normal libcall code path is
used on soft ABIs).

The extend operation is implemented by a shift just as in the standard
legalisation, but needs to be custom lowered because i32 isn't a legal
type on RV64.

This patch aims to make the minimal changes that result in correct
codegen for the bfloat.ll tests.

Differential Revision: https://reviews.llvm.org/D151663

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[RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs

This results in improved codegen for half/bf16 libcalls on soft ABIs

Adds a RISCVSubtarget helper method

[RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs

This results in improved codegen for half/bf16 libcalls on soft ABIs

Adds a RISCVSubtarget helper method for determining if a soft FP ABI is
being targeted (future bf16 related patches make use of this).

Differential Revision: https://reviews.llvm.org/D151434

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[RISCV][test] Expand bfloat.ll tests to include i16 bitcasts and load/store

Pre-commit new tests used in D151663.

[SelectionDAG] Implement soft FP legalisation for bf16 FP_EXTEND and BF16_TO_FP

As discussed in D151436, it's safe to do this as a simple shift (as is
done in LegalizeDAG.cpp) rather than needing a

[SelectionDAG] Implement soft FP legalisation for bf16 FP_EXTEND and BF16_TO_FP

As discussed in D151436, it's safe to do this as a simple shift (as is
done in LegalizeDAG.cpp) rather than needing a libcall. The added test
cases for RISC-V previously just triggered an assertion.

Codegen for bfloat_to_double will be slightly improved by D151434.

Differential Revision: https://reviews.llvm.org/D151563

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