[RISCV] Add Smrnmi extension (#111668)

This commit has completed the Extension for Resumable Non Maskable
Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:["Smrnmi"

[RISCV] Add Smrnmi extension (#111668)

This commit has completed the Extension for Resumable Non Maskable
Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:["Smrnmi"
Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc)

---------

Co-authored-by: Sam Elliott <sam@lenary.co.uk>

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[RISCV] Mark Zacas as non-experimental (#109651)

The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-do

[RISCV] Mark Zacas as non-experimental (#109651)

The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.

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[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3

[RISCV] Remove experimental for Ssqosid ext (#105476)

Ratified: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0

[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instr

[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.

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[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)

As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com

[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)

As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>.

Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.

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[RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 (#98891)

Both of them are ratified now.
https://wiki.riscv.org/display/HOME/Ratified+Extensions

This patch does not set them to non-experimenta

[RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 (#98891)

Both of them are ratified now.
https://wiki.riscv.org/display/HOME/Ratified+Extensions

This patch does not set them to non-experimental, since Zicfilp lacks
lld support and Zicfiss also lacks compiler-rt/libunwind support.

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[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.

As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.

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Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that,
the default WMO lowering has moved to A67 compatible, the ABI at

Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that,
the default WMO lowering has moved to A67 compatible, the ABI attribute
emission has landed (off by default), and the LLD change to merge said
attributes have landed. Our ztso lowering is believed to also be A67
compatible, and no known issues remain.

Original commit message:

Ztso 1.0 was ratified in January 2023.
Documentation:
https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc

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[RISCV] Remove experimental for bf16 extensions (#97996)

They are already ratified now.

Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the def

Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation
in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc

This patch changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.

This was reverted with https://github.com/llvm/llvm-project/pull/84597,
because ld.bfd would segfault with unknown riscv attributes. Now that
attributes emission is guarded with a backend flag,
`--riscv-abi-attributes`, this should be safe to reland, since it won't
introduce abi tags unless the user opts into them.

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Reapply "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This patch adds support for the atomic_abi attribute, specifid in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/ris

Reapply "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This patch adds support for the atomic_abi attribute, specifid in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version.

This was previously reverted due to ld.bfd segfaulting w/ unknown riscv
attributes. Attribute emission is now guarded by a backend flag
`--riscv-abi-attributes`, which is off by default. Linker support in
LLD for attribute merging is now in a standalone patch.

Reviewers: kito-cheng, MaskRay, asb

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/90266

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[RISCV] Bump Pointer Masking extension version (#96715)

These extensions had their version number bumped and still experimental
(under public review). I didn't see anything in the [commit
history]

[RISCV] Bump Pointer Masking extension version (#96715)

These extensions had their version number bumped and still experimental
(under public review). I didn't see anything in the [commit
history](https://github.com/riscv/riscv-j-extension/commits/master/)
since #79929 that would warrant a change to the implementation of
pointer masking in the compiler.

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Revert "[RISCV] Remove experimental from Ztso. (#96465)"

This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See
discussion on review thread.

[RISCV] Remove experimental from Ztso. (#96465)

Ztso 1.0 was ratified in January 2023.
Documentation:
https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc

[RISCV] Make M imply Zmmul (#95070)

According to the spec, M implies Zmmul.

[RISCV] Add Smcsrind and Sscsrind extension (#93952)

Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc


Some CSRs (`*ireg` and `*iselect`) in Smcsrin

[RISCV] Add Smcsrind and Sscsrind extension (#93952)

Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc


Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are
originally defined as part of the Smaia/Ssaia extensions and are already
supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`,
and `vs`) are added in this PR.

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[RISCV] Add smcdeleg and ssccfg extensions (#95163)

Specification:
https://github.com/riscv/riscv-isa-manual/blob/main/src/smcdeleg.adoc

`Ssccfg` introduces one new CSR `scountinhibit`.

[RISCV] Add B extension (#76893)

It seems that we have `B` extension again:
https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs

[RISCV] Add B extension (#76893)

It seems that we have `B` extension again:
https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.

Though it hasn't been ratified, I set its version to `1.0`.

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[RISCV] Remove experimental from Zabha (#93831)

The Zabha extension was ratified in April 2024.

Co-authored-by: Alexandre Ghiti <alexghiti@rivosinc.com>

[RISCV] Zicfilp implies Zicsr. (#93143)

The Zicfilp extension depends on the Zicsr extension.
Ref: https://github.com/riscv/riscv-cfi/blob/main/src/cfi_forward.adoc

[RISCV] Bump Zaamo and Zalrsc to version 1.0 (#91556)

The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions

[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167)

As discussed in the last sync-up call, because these profiles are not
yet finalised they shouldn't be exposed to us

[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167)

As discussed in the last sync-up call, because these profiles are not
yet finalised they shouldn't be exposed to users unless they opt-in to
them (much like experimental extensions). We may later want to add a
more specific flag, but reusing `-menable-experimental-extensions`
solves the immediate problem.

This is implemented using the new support for marking profiles s
experimental added in #91993 to move the unratified profiles to
RISCVExperimentalProfile and making the necessary changes to logic in
RISCVISAInfo to handle this.

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[RISCV] Add smstateen extension (#90818)

[RISCV] Add subtarget features for profiles

This may simplify the usage of tools like `opt`, `llc`, etc.

Reviewers: michaelmaitland, 4vtomat, preames, asb

Reviewed By: michaelmaitland, preames, 4v

[RISCV] Add subtarget features for profiles

This may simplify the usage of tools like `opt`, `llc`, etc.

Reviewers: michaelmaitland, 4vtomat, preames, asb

Reviewed By: michaelmaitland, preames, 4vtomat

Pull Request: https://github.com/llvm/llvm-project/pull/84877

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