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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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329b8cd3 |
| 04-Jul-2023 |
Nemanja Ivanovic <nemanja.i.ibm@gmail.com> |
[PowerPC] Improve code gen for vector add
Improve codegen for vectors modulo additions.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D154447
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c7c3d714 |
| 04-Jul-2023 |
Lei Huang <lei@ca.ibm.com> |
[PowerPC] add testcase for vector add and shift
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