[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

This addresses the following issue I opened:
https://github.com/llvm/llvm-project/issues/118851.

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

This addresses the following issue I opened:
https://github.com/llvm/llvm-project/issues/118851.

This change generalizes the Type Legalization mechanism that currently
handles `v8[i/f/bf]16` upsizing to include loads _and_ stores of `v8i8`
+ `v16i8`, allowing all of the mentioned vectors to be lowered to ptx as
vectors of `b32`. This extension also allows us to remove the DagCombine
that only handled exactly `load v16i8`, thus centralizing all the
upsizing logic into one place.

Test changes include adding v8i8, v16i8, and v8i16 cases to
load-store.ll, and updating the CHECKs for other tests to match the
improved codegen.

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