History log of /llvm-project/llvm/test/CodeGen/AArch64/insertshuffleload.ll (Results 1 – 5 of 5)
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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6
# 61510b51 12-Dec-2024 Sander de Smalen <sander.desmalen@arm.com>

Revert "[AArch64] Enable subreg liveness tracking by default."

This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.

Some issues were discovered with the bootstrap builds, which
seem like t

Revert "[AArch64] Enable subreg liveness tracking by default."

This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.

Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.

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Revision tags: llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3
# 9c319d5b 15-Oct-2024 Sander de Smalen <sander.desmalen@arm.com>

[AArch64] Enable subreg liveness tracking by default.

Internal testing didn't flag up any functional- or performance regressions.


Revision tags: llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1
# db158c7c 28-Jul-2023 Harvin Iriawan <harvin.iriawan@arm.com>

[AArch64] Update generic sched model to A510

Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.

[AArch64] Update generic sched model to A510

Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
Changes tested on various OoO cores, no performance degradation is seen.

Differential Revision: https://reviews.llvm.org/D156799

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Revision tags: llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5
# 7740216f 31-May-2023 David Green <david.green@arm.com>

[DAG] Combine insert(shuffle(load), load, 0) into a single load

Given an insert of a scalar load into a vector shuffle with mask
u,0,1,2,3,4,5,6 or 1,2,3,4,5,6,7,u (depending on the insert index),
i

[DAG] Combine insert(shuffle(load), load, 0) into a single load

Given an insert of a scalar load into a vector shuffle with mask
u,0,1,2,3,4,5,6 or 1,2,3,4,5,6,7,u (depending on the insert index),
it can be more profitable to convert to a single load and avoid the
shuffles. This adds a DAG combine for it, providing the new load is
still fast.

Differential Revision: https://reviews.llvm.org/D151029

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# 8d82f12a 31-May-2023 David Green <david.green@arm.com>

[ARM][AArch64] Add tests for shuffles load patterns. NFC

See D151029