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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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16e05919 |
| 22-Jul-2024 |
AtariDreams <gfunni234@gmail.com> |
[AArch64] Use isKnownNonZero to optimize eligible compares to cmn and ccmn (#96349)
The problematic case for unsigned comparisons occurs only when the
second argument is zero.
The problematic ca
[AArch64] Use isKnownNonZero to optimize eligible compares to cmn and ccmn (#96349)
The problematic case for unsigned comparisons occurs only when the
second argument is zero.
The problematic case for signed comparisons occurs only when the second
argument is the signed minimum value.
We can use KnownBits to know when we don't have to worry about this.
Source: https://devblogs.microsoft.com/oldnewthing/20210607-00/?p=105288
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4e6835d4 |
| 21-Jun-2024 |
AtariDreams <gfunni234@gmail.com> |
[AArch64] Use ccmn to compare negative immediates between -1 and -31 (#95825)
Because ccmn is like a + b, it works when using cmp but with values that
when negated are in the range of 1 through 31
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4 |
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ebb64d83 |
| 26-Feb-2024 |
Owen Anderson <resistor@mac.com> |
[GlobalISel] Make the Combiner insert G_FREEZE when converting G_SELECT to binary operations. (#82733)
This is needed because the binary operators (G_OR and G_AND) do
not have the poison-suppressing
[GlobalISel] Make the Combiner insert G_FREEZE when converting G_SELECT to binary operations. (#82733)
This is needed because the binary operators (G_OR and G_AND) do
not have the poison-suppressing semantics of G_SELECT.
Fixes https://github.com/llvm/llvm-project/issues/72475
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Revision tags: llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1 |
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db158c7c |
| 28-Jul-2023 |
Harvin Iriawan <harvin.iriawan@arm.com> |
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
Changes tested on various OoO cores, no performance degradation is seen.
Differential Revision: https://reviews.llvm.org/D156799
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Revision tags: llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6 |
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6a353c77 |
| 27-Nov-2022 |
David Green <david.green@arm.com> |
[AArch64] Add GPR rr instructions to isAssociativeAndCommutative
This adds some more scalar instructions that are both associative and
commutative to isAssociativeAndCommutative, allowing the machin
[AArch64] Add GPR rr instructions to isAssociativeAndCommutative
This adds some more scalar instructions that are both associative and
commutative to isAssociativeAndCommutative, allowing the machine
combiner to reassociate them to reduce critical path length.
Differential Revision: https://reviews.llvm.org/D134260
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8f104b80 |
| 22-Nov-2022 |
Vitaly Buka <vitalybuka@google.com> |
Revert "[AArch64] Add GPR rr instructions to isAssociativeAndCommutative"
Breaks msan on aarch64.
This reverts commit 5f7f484ee54ebbf702ee4c5fe9852502dc237121.
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5f7f484e |
| 16-Nov-2022 |
David Green <david.green@arm.com> |
[AArch64] Add GPR rr instructions to isAssociativeAndCommutative
This adds some more scalar instructions that are both associative and
commutative to isAssociativeAndCommutative, allowing the machin
[AArch64] Add GPR rr instructions to isAssociativeAndCommutative
This adds some more scalar instructions that are both associative and
commutative to isAssociativeAndCommutative, allowing the machine
combiner to reassociate them to reduce critical path length.
Differential Revision: https://reviews.llvm.org/D134260
show more ...
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Revision tags: llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2 |
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6ff873ac |
| 04-Aug-2022 |
David Green <david.green@arm.com> |
[AArch64] Add some extra GlobalISel CCMP tests coverage. NFC
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Revision tags: llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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43a0016f |
| 16-Feb-2022 |
Karl Meakin <karl.meakin@arm.com> |
Extend `performANDCSELCombine` to `performANDORCSELCombine`
Differential Revision: https://reviews.llvm.org/D120422
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