|
Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1 |
|
| #
db158c7c |
| 28-Jul-2023 |
Harvin Iriawan <harvin.iriawan@arm.com> |
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
Changes tested on various OoO cores, no performance degradation is seen.
Differential Revision: https://reviews.llvm.org/D156799
show more ...
|
|
Revision tags: llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
|
| #
07d6af6a |
| 09-Jan-2023 |
David Green <david.green@arm.com> |
[AArch64] Fold And/Or into CSel if possible
If we have `and x, (csel 0, 1, cc)` and we know that x is 0/1, then we
can emit a `csel ZR, x, cc`. Similarly for `or x, (csel 0, 1, cc)` we
can emit `csi
[AArch64] Fold And/Or into CSel if possible
If we have `and x, (csel 0, 1, cc)` and we know that x is 0/1, then we
can emit a `csel ZR, x, cc`. Similarly for `or x, (csel 0, 1, cc)` we
can emit `csinc x, ZR, cc`. This can help where we can not otherwise
general ccmp instructions.
Differential Revision: https://reviews.llvm.org/D141119
show more ...
|
|
Revision tags: llvmorg-15.0.6 |
|
| #
3651bc83 |
| 23-Nov-2022 |
zhongyunde <zhongyunde@huawei.com> |
[AArch64] Optimize cmp chain before legalization
* For case bcmp9, there is extras AND and EXTEND int the chain of OR/XOR,
which prevent the transform, so enable the optimize before legalization.
[AArch64] Optimize cmp chain before legalization
* For case bcmp9, there is extras AND and EXTEND int the chain of OR/XOR,
which prevent the transform, so enable the optimize before legalization.
* The key IR frag related:
t37: i32,ch = load<(load (s8) from %ir.4), anyext from i8> t0, t11, undef:i64
t12: i64 = add t4, Constant:i64<8>
t38: i32,ch = load<(load (s8) from %ir.5), anyext from i8> t0, t12, undef:i64
t39: i32 = xor t37, t38
t40: i64 = any_extend t39
t42: i64 = and t40, Constant:i64<255>
Depends on D138398 to fix combine_setcc_glue
Reviewed By: dmgreen, bcl5980
Differential Revision: https://reviews.llvm.org/D137936
show more ...
|
|
Revision tags: llvmorg-15.0.5 |
|
| #
894f9e54 |
| 13-Nov-2022 |
zhongyunde <zhongyunde@huawei.com> |
[AArch64] Optimize more memcmp when the result is tested for [in]equality with 0
We already surpport the or (xor a, b), (xor c, d) with D136244, while it should
capture more cases than just bcmp acc
[AArch64] Optimize more memcmp when the result is tested for [in]equality with 0
We already surpport the or (xor a, b), (xor c, d) with D136244, while it should
capture more cases than just bcmp according the comment on
https://reviews.llvm.org/D136672, so this patch try to fold continuous
comparison series.
Also add a new callsite in LowerSETCC to address some cases folded And in the
stage of `Optimized type-legalized selection`.
Depends on D136244
Reviewed By: dmgreen, bcl5980
Differential Revision: https://reviews.llvm.org/D137721
show more ...
|
|
Revision tags: llvmorg-15.0.4 |
|
| #
63a46385 |
| 29-Oct-2022 |
zhongyunde <zhongyunde@huawei.com> |
Recommit [AArch64] Optimize memcmp when the result is tested for [in]equality with 0
Fixes 1st issue of https://github.com/llvm/llvm-project/issues/58061
Fixes the crash of https://github.com/llvm/l
Recommit [AArch64] Optimize memcmp when the result is tested for [in]equality with 0
Fixes 1st issue of https://github.com/llvm/llvm-project/issues/58061
Fixes the crash of https://github.com/llvm/llvm-project/issues/58675
Reviewed By: dmgreen, efriedma
Differential Revision: https://reviews.llvm.org/D136244
show more ...
|
| #
1c068175 |
| 28-Oct-2022 |
Paul Kirth <paulkirth@google.com> |
Revert "[AArch64] Optimize memcmp when the result is tested for [in]equality with 0"
This reverts commit 01ff511593d1a4920fa3c1d450ad2077661e0bdc.
It triggers an assertion failure in SelectionDAG.c
Revert "[AArch64] Optimize memcmp when the result is tested for [in]equality with 0"
This reverts commit 01ff511593d1a4920fa3c1d450ad2077661e0bdc.
It triggers an assertion failure in SelectionDAG.cpp
see https://github.com/llvm/llvm-project/issues/58675 for details.
show more ...
|
| #
01ff5115 |
| 27-Oct-2022 |
zhongyunde <zhongyunde@huawei.com> |
[AArch64] Optimize memcmp when the result is tested for [in]equality with 0
Fixes 1st issue of https://github.com/llvm/llvm-project/issues/58061
Reviewed By: dmgreen, efriedma
Differential Revision
[AArch64] Optimize memcmp when the result is tested for [in]equality with 0
Fixes 1st issue of https://github.com/llvm/llvm-project/issues/58061
Reviewed By: dmgreen, efriedma
Differential Revision: https://reviews.llvm.org/D136244
show more ...
|
| #
e95c74b4 |
| 25-Oct-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Add precommit test for bcmp; NFC
|