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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7 |
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| #
deab451e |
| 04-Jun-2024 |
Nikita Popov <npopov@redhat.com> |
[IR] Remove support for icmp and fcmp constant expressions (#93038)
Remove support for the icmp and fcmp constant expressions.
This is part of:
https://discourse.llvm.org/t/rfc-remove-most-const
[IR] Remove support for icmp and fcmp constant expressions (#93038)
Remove support for the icmp and fcmp constant expressions.
This is part of:
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179
As usual, many of the updated tests will no longer test what they were
originally intended to -- this is hard to preserve when constant
expressions get removed, and in many cases just impossible as the
existence of a specific kind of constant expression was the cause of the
issue in the first place.
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Revision tags: llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3 |
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| #
25e7e8d9 |
| 20-Feb-2024 |
Antonio Frighetto <me@antoniofrighetto.com> |
[CGP] Permit tail call optimization on undefined return value
We may freely allow tail call optzs on undef values as well.
Fixes: https://github.com/llvm/llvm-project/issues/82387.
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|
Revision tags: llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1 |
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| #
db158c7c |
| 28-Jul-2023 |
Harvin Iriawan <harvin.iriawan@arm.com> |
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information.
[AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen.
Differential Revision: https://reviews.llvm.org/D156799
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Revision tags: llvmorg-18-init |
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| #
6e54fcce |
| 01-Jul-2023 |
Igor Kudrin <ikudrin@accesssoftek.com> |
[AArch64] Emit fewer CFI instructions for synchronous unwind tables
The instruction-precise, or asynchronous, unwind tables usually take up much more space than the synchronous ones. If a user is co
[AArch64] Emit fewer CFI instructions for synchronous unwind tables
The instruction-precise, or asynchronous, unwind tables usually take up much more space than the synchronous ones. If a user is concerned about the load size of the program and does not need the features provided with the asynchronous tables, the compiler should be able to generate the more compact variant.
This patch changes the generation of CFI instructions for these cases so that they all come in one chunk in the prolog; it emits only one `.cfi_def_cfa*` instruction followed by `.cfi_offset` ones after all stack adjustments and register spills, and avoids generating CFI instructions in the epilog(s) as well as any other exceeding CFI instructions like `.cfi_remember_state` and `.cfi_restore_state`. Effectively, it reverses the effects of D111411 and D114545 on functions with the `uwtable(sync)` attribute. As a side effect, it also restores the behavior on functions that have neither `uwtable` nor `nounwind` attributes.
Differential Revision: https://reviews.llvm.org/D153098
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4 |
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| #
4e2b4f97 |
| 03-May-2023 |
Florian Hahn <flo@fhahn.com> |
[ShrinkWrap] Use underlying object to rule out stack access.
Allow shrink-wrapping past memory accesses that only access globals or function arguments. This patch uses getUnderlyingObject to try to
[ShrinkWrap] Use underlying object to rule out stack access.
Allow shrink-wrapping past memory accesses that only access globals or function arguments. This patch uses getUnderlyingObject to try to identify the accessed object by a given memory operand. If it is a global or an argument, it does not access the stack of the current function and should not block shrink wrapping.
Note that the caller's stack may get accessed when passing an argument via the stack, but not the stack of the current function.
This addresses part of the TODO from D63152.
Reviewed By: thegameg
Differential Revision: https://reviews.llvm.org/D149668
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|
Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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| #
5ddce70e |
| 19-Dec-2022 |
Nikita Popov <npopov@redhat.com> |
[AArch64] Convert some tests to opaque pointers (NFC)
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|
Revision tags: llvmorg-15.0.6, llvmorg-15.0.5 |
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| #
a3623128 |
| 09-Nov-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Support all extend/shift op for pattern: (ExtendOrShfitNode - Y) + Z --> (Z - Y) + ExtendOrShfitNode
Followup rG325a3083b5b24 Add SRL/SRA/xxx_EXTEND/AND support
Reviewed By: dmgreen
Diff
[AArch64] Support all extend/shift op for pattern: (ExtendOrShfitNode - Y) + Z --> (Z - Y) + ExtendOrShfitNode
Followup rG325a3083b5b24 Add SRL/SRA/xxx_EXTEND/AND support
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D137069
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| #
000588d9 |
| 09-Nov-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Precommit test for D137069; NFC
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| #
7f26693f |
| 08-Nov-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
Revert "[AArch64] Precommit test for D137069; NFC"
This reverts commit 281f2134a730f147428d75c09a28f0c5e1be95d9.
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| #
281f2134 |
| 08-Nov-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Precommit test for D137069; NFC
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Revision tags: llvmorg-15.0.4 |
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| #
325a3083 |
| 31-Oct-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift
((X >> C) - Y) + Z --> (Z - Y) + (X >> C)
Fix AArch part: #55714
Reviewed By: dmgreen
Differential Revision: https://rev
[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift
((X >> C) - Y) + Z --> (Z - Y) + (X >> C)
Fix AArch part: #55714
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136158
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| #
dfb16bd5 |
| 28-Oct-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
Revert "[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift"
This reverts commit ada9ab610727917561370e976eaea26dbbc20cce.
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| #
ada9ab61 |
| 27-Oct-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift
((X >> C) - Y) + Z --> (Z - Y) + (X >> C)
Fix AArch part: #55714
Reviewed By: dmgreen
Differential Revision: https://rev
[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift
((X >> C) - Y) + Z --> (Z - Y) + (X >> C)
Fix AArch part: #55714
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136158
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| #
327c45da |
| 18-Oct-2022 |
chenglin.bi <chenglin.bi@linaro.org> |
[AArch64] add test case for pattern ((X >> C) - Y) + Z; NFC
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Revision tags: llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1 |
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| #
6a2442e9 |
| 06-Sep-2022 |
Alexander Shaposhnikov <ashaposhnikov@google.com> |
[AArch64] Increase AddedComplexity of BIC
This diff adjusts AddedComplexity of BIC to bump its position in the list of patterns to make LLVM pick it instead of MVN + AND. MVN + AND requires 2 cycles
[AArch64] Increase AddedComplexity of BIC
This diff adjusts AddedComplexity of BIC to bump its position in the list of patterns to make LLVM pick it instead of MVN + AND. MVN + AND requires 2 cycles, so does e.g. MOV + BIC, but the latter outperforms the former if the instructions producing the operands of BIC can be issued in parallel.
One may consider the following example:
ldur x15, [x0, #2] # 4 cycles mvn x10, x15 # 1 cycle (depends on ldur) and x9, x10, #0x8080808080808080
vs.
ldur x15, [x0, #2] # 4 cycles mov x9, #0x8080808080808080 # 1 cycle (can be executed in parallel with ldur) bic x9, x9, x15. # 1 cycle
Test plan: ninja check-all
Differential revision: https://reviews.llvm.org/D133345
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|
Revision tags: llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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| #
c69af70f |
| 19-Feb-2022 |
Micah Weston <micahsweston@gmail.com> |
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
Implements ADDS/SUBS 24-bit immediate optimization using the MIPeepholeOpt pass. This follows the pattern:
Optimize ([adds|subs] r, i
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
Implements ADDS/SUBS 24-bit immediate optimization using the MIPeepholeOpt pass. This follows the pattern:
Optimize ([adds|subs] r, imm) -> ([ADDS|SUBS] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Optimize ([adds|subs] r, imm) -> ([SUBS|ADDS] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers.
The SplitAndOpcFunc type had to change the return type to an Opcode pair so that the first add/sub is the regular instruction and the second is the flag setting instruction. This required updating the code in the AND case.
Testing:
I ran a two stage bootstrap with this code. Using the second stage compiler, I verified that the negation of an ADDS to SUBS or vice versa is a valid optimization. Example V == -0x111111.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D118663
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| #
22eb1dae |
| 13-Feb-2022 |
Nathan Chancellor <nathan@kernel.org> |
Revert "[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt."
This reverts commit af45d0fd94b21620b61c8c4900b81486fd85aeb7.
This causes assertions failures when compiling the Linux kerne
Revert "[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt."
This reverts commit af45d0fd94b21620b61c8c4900b81486fd85aeb7.
This causes assertions failures when compiling the Linux kernel. See https://reviews.llvm.org/D118663 for a reduced reproducer.
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| #
af45d0fd |
| 12-Feb-2022 |
Micah Weston <micahsweston@gmail.com> |
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
Implements ADDS/SUBS 24-bit immediate optimization using the MIPeepholeOpt pass. This follows the pattern:
Optimize ([adds|subs] r, i
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
Implements ADDS/SUBS 24-bit immediate optimization using the MIPeepholeOpt pass. This follows the pattern:
Optimize ([adds|subs] r, imm) -> ([ADDS|SUBS] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Optimize ([adds|subs] r, imm) -> ([SUBS|ADDS] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers.
The SplitAndOpcFunc type had to change the return type to an Opcode pair so that the first add/sub is the regular instruction and the second is the flag setting instruction. This required updating the code in the AND case.
Testing:
I ran a two stage bootstrap with this code. Using the second stage compiler, I verified that the negation of an ADDS to SUBS or vice versa is a valid optimization. Example V == -0x111111.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D118663
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|
Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init |
|
| #
f65651cc |
| 26-Jan-2022 |
Micah Weston <micahsweston@gmail.com> |
[AArch64] Fixes ADD/SUB opt bug and abstracts shared behavior in MIPeepholeOpt for ADD, SUB, and AND.
This fixes a bug where (SUBREG_TO_REG 0 (MOVi32imm <negative-number>) sub_32) would generate inv
[AArch64] Fixes ADD/SUB opt bug and abstracts shared behavior in MIPeepholeOpt for ADD, SUB, and AND.
This fixes a bug where (SUBREG_TO_REG 0 (MOVi32imm <negative-number>) sub_32) would generate invalid code since the top 32-bits were not zeroed when inspecting the immediate value. A new test was added for this case.
Change to abstract shared behavior in MIPeepholeOpt. Both visitAND and visitADDSUB attempt to split an RR instruction with an immediate operand into two RI instructions with the immediate split.
The differing behavior lies in how the immediate is split into two pieces and how the new instructions are built. The rest of the behavior (adding new VRegs, checking for the MOVImm, constraining reg classes, removing old intructions) are shared between the operations.
The new helper function splitTwoPartImm implements the shared behavior and delegates differing behavior to two function objects passed by the caller. One function object splits the immediate into two values and returns the opcode to use if it is a valid split. The other function object builds the new instructions.
I felt this abstraction would help since I believe it will help reduce the code repetition when adding new instructions of the pattern, such as SUBS for this conditional optimization.
Tested it locally by running check all with compiler-rt, mlir, clang-tools-extra, flang, llvm, and clang enabled.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D118000
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| #
93deac2e |
| 22-Jan-2022 |
Micah Weston <micahsweston@gmail.com> |
[AArch64] Optimize add/sub with immediate through MIPeepholeOpt
Fixes the build issue with D111034, whose goal was to optimize add/sub with long immediates.
Optimize ([add|sub] r, imm) -> ([ADD|SUB
[AArch64] Optimize add/sub with immediate through MIPeepholeOpt
Fixes the build issue with D111034, whose goal was to optimize add/sub with long immediates.
Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Optimize ([add|sub] r, imm) -> ([SUB|ADD] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers.
The change which fixed the build issue in D111034 was the use of new virtual registers so that SSA form is maintained until deleting MI.
Differential Revision: https://reviews.llvm.org/D117429
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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| #
62476c7c |
| 18-Jan-2022 |
Florian Hahn <flo@fhahn.com> |
Revert "[AArch64] Revive optimize add/sub with immediate through MIPeepholeOpt"
This reverts commit e6698f09929a134bf0f46d9347142b86d8f636a2.
This commit appears to introduce new machine verifier f
Revert "[AArch64] Revive optimize add/sub with immediate through MIPeepholeOpt"
This reverts commit e6698f09929a134bf0f46d9347142b86d8f636a2.
This commit appears to introduce new machine verifier failures when building the llvm-test-suite with `-mllvm -verify-machineinstrs` enabled:
https://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-aarch64-O3/11061/
FAILED: MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/test-suite-build/tools/timeit --summary MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o.time /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/compiler/bin/clang -DNDEBUG -B /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin -Wno-unused-command-line-argument -mllvm -verify-machineinstrs -O3 -arch arm64 -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS13.5.sdk -w -Werror=date-time -DTORONTO -MD -MT MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o -MF MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o.d -o MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o -c /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/test-suite/MultiSource/Benchmarks/Olden/health/health.c *** Bad machine code: Illegal virtual register for instruction *** - function: alloc_tree - basic block: %bb.1 if.else (0x7fc0db8f8bb0) - instruction: %31:gpr64 = nsw MADDXrrr killed %39:gpr64sp, killed %25:gpr64, $xzr - operand 1: killed %39:gpr64sp Expected a GPR64 register, but got a GPR64sp register fatal error: error in backend: Found 1 machine code errors. PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script. Stack dump: 0. Program arguments: /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/compiler/bin/clang -DNDEBUG -B /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin -Wno-unused-command-line-argument -mllvm -verify-machineinstrs -O3 -arch arm64 -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS13.5.sdk -w -Werror=date-time -DTORONTO -MD -MT MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o -MF MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o.d -o MultiSource/Benchmarks/Olden/health/CMakeFiles/health.dir/health.c.o -c /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/test-suite/MultiSource/Benchmarks/Olden/health/health.c 1. <eof> parser at end of file 2. Code generation 3. Running pass 'Function Pass Manager' on module '/Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/test-suite/MultiSource/Benchmarks/Olden/health/health.c'. 4. Running pass 'Verify generated machine code' on function '@alloc_tree' Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it): 0 clang 0x000000011191896b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 43 1 clang 0x00000001119179b5 llvm::sys::RunSignalHandlers() + 85 2 clang 0x00000001119180e2 llvm::sys::CleanupOnSignal(unsigned long) + 210 3 clang 0x0000000111849f6a (anonymous namespace)::CrashRecoveryContextImpl::HandleCrash(int, unsigned long) + 106 4 clang 0x0000000111849ee8 llvm::CrashRecoveryContext::HandleExit(int) + 24 5 clang 0x0000000111914acc llvm::sys::Process::Exit(int, bool) + 44 6 clang 0x000000010f4e9be9 LLVMErrorHandler(void*, char const*, bool) + 89 7 clang 0x0000000114eba333 llvm::report_fatal_error(llvm::Twine const&, bool) + 323 8 clang 0x0000000110d8c620 (anonymous namespace)::MachineVerifier::BBInfo::~BBInfo() + 0 9 clang 0x0000000110cdddca llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 378 10 clang 0x00000001110b0154 llvm::FPPassManager::runOnFunction(llvm::Function&) + 1092 11 clang 0x00000001110b6268 llvm::FPPassManager::runOnModule(llvm::Module&) + 72 12 clang 0x00000001110b074a llvm::legacy::PassManagerImpl::run(llvm::Module&) + 986 13 clang 0x0000000111c20ad4 clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, std::__1::unique_ptr<llvm::raw_pwrite_stream, std::__1::default_delete<llvm::raw_pwrite_stream> >) + 3764 14 clang 0x0000000111f6dd31 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) + 1905 15 clang 0x00000001131a28b3 clang::ParseAST(clang::Sema&, bool, bool) + 643 16 clang 0x00000001122b02a4 clang::FrontendAction::Execute() + 84 17 clang 0x000000011222d6a9 clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 873 18 clang 0x000000011232faf5 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 661 19 clang 0x000000010f4e9860 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) + 2544 20 clang 0x000000010f4e7168 ExecuteCC1Tool(llvm::SmallVectorImpl<char const*>&) + 312 21 clang 0x00000001120ab187 void llvm::function_ref<void ()>::callback_fn<clang::driver::CC1Command::Execute(llvm::ArrayRef<llvm::Optional<llvm::StringRef> >, std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >*, bool*) const::$_1>(long) + 23 22 clang 0x0000000111849eb4 llvm::CrashRecoveryContext::RunSafely(llvm::function_ref<void ()>) + 228 23 clang 0x00000001120aac24 clang::driver::CC1Command::Execute(llvm::ArrayRef<llvm::Optional<llvm::StringRef> >, std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >*, bool*) const + 324 24 clang 0x000000011207b85d clang::driver::Compilation::ExecuteCommand(clang::driver::Command const&, clang::driver::Command const*&) const + 221 25 clang 0x000000011207bdad clang::driver::Compilation::ExecuteJobs(clang::driver::JobList const&, llvm::SmallVectorImpl<std::__1::pair<int, clang::driver::Command const*> >&) const + 125 26 clang 0x0000000112092f7c clang::driver::Driver::ExecuteCompilation(clang::driver::Compilation&, llvm::SmallVectorImpl<std::__1::pair<int, clang::driver::Command const*> >&) + 204 27 clang 0x000000010f4e6977 main + 10375 28 libdyld.dylib 0x00007fff6be90cc9 start + 1 29 libdyld.dylib 0x0000000000000018 start + 18446603338705728336 clang-14: error: clang frontend command failed with exit code 70 (use -v to see invocation) clang version 14.0.0 (https://github.com/llvm/llvm-project.git c90d136be4e055f1b409f38706d0fe3e2211af08) Target: arm64-apple-darwin19.5.0 Thread model: posix InstalledDir: /Users/buildslave/jenkins/workspace/test-suite-verify-machineinstrs-aarch64-O3/compiler/bin clang-14: note: diagnostic msg: ********************
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|
| #
e6698f09 |
| 17-Jan-2022 |
Micah Weston <micahsweston@gmail.com> |
[AArch64] Revive optimize add/sub with immediate through MIPeepholeOpt
Fixes the build issue with D111034, whose goal was to optimize add/sub with long immediates.
Optimize ([add|sub] r, imm) -> ([
[AArch64] Revive optimize add/sub with immediate through MIPeepholeOpt
Fixes the build issue with D111034, whose goal was to optimize add/sub with long immediates.
Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Optimize ([add|sub] r, imm) -> ([SUB|ADD] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers.
The change which fixed the build issue in D111034 was the use of new virtual registers so that SSA form is maintained until deleting MI.
Differential Revision: https://reviews.llvm.org/D117429
show more ...
|
|
Revision tags: llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
|
| #
59c3b48d |
| 03-Nov-2021 |
Ben Shi <powerman1st@163.com> |
Revert "[AArch64] Optimize add/sub with immediate"
This reverts commit 3de3ca3137bec5115cd10c53f4059f9bf1054e96.
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3de3ca31 |
| 01-Nov-2021 |
Ben Shi <powerman1st@163.com> |
[AArch64] Optimize add/sub with immediate
Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsig
[AArch64] Optimize add/sub with immediate
Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Optimize ([add|sub] r, imm) -> ([SUB|ADD] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers.
Reviewed By: jaykang10, dmgreen
Differential Revision: https://reviews.llvm.org/D111034
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d0dbc991 |
| 16-Oct-2021 |
Ben Shi <powerman1st@163.com> |
Revert "[AArch64] Optimize add/sub with immediate"
This reverts commit 9bf6bef9951a1c230796ccad2c5c0195ce4c4dff.
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