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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4 |
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b71edfaa |
| 15-May-2023 |
Tobias Hieta <tobias@hieta.se> |
[NFC][Py Reformat] Reformat python files in llvm
This is the first commit in a series that will reformat
all the python files in the LLVM repository.
Reformatting is done with `black`.
See more in
[NFC][Py Reformat] Reformat python files in llvm
This is the first commit in a series that will reformat
all the python files in the LLVM repository.
Reformatting is done with `black`.
See more information here:
https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style
Reviewed By: jhenderson, JDevlieghere, MatzeB
Differential Revision: https://reviews.llvm.org/D150545
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Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2 |
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| #
9e3010ad |
| 07-Feb-2023 |
Tomas Matheson <tomas.matheson@arm.com> |
[AArch64] Fix LSE2/LSE128/RCPC3 precedence
D142712 added tests for when both lse2 and lse128 are available, but
in practice there is no way to enable LSE128 without LSE2 from clang:
LSE128 is a v9 o
[AArch64] Fix LSE2/LSE128/RCPC3 precedence
D142712 added tests for when both lse2 and lse128 are available, but
in practice there is no way to enable LSE128 without LSE2 from clang:
LSE128 is a v9 only feature and LSE2 has been mandatory since v8.4,
and +/-lse2 can not be specified on the clang command line.
Therefore it makes more sense that lse2+lse128 should emit lse128
instructions, otherwise they will not be emitted at all.
It also makes sense to remove the lse128-only backend tests if that set
of attributes is never set by the frontend.
Differential Revision: https://reviews.llvm.org/D143506
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Revision tags: llvmorg-16.0.0-rc1 |
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| #
5a9cb377 |
| 27-Jan-2023 |
Tomas Matheson <tomas.matheson@arm.com> |
[AArch64] Add atomics tests for lse2+lse128
FEAT_LSE128 implies FEAT_LSE but not FEAT_LSE2, so add tests showing
what happens when you have both.
Differential Revision: https://reviews.llvm.org/D14
[AArch64] Add atomics tests for lse2+lse128
FEAT_LSE128 implies FEAT_LSE but not FEAT_LSE2, so add tests showing
what happens when you have both.
Differential Revision: https://reviews.llvm.org/D142712
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| #
7c84f94e |
| 25-Jan-2023 |
Tomas Matheson <tomas.matheson@arm.com> |
[AArch64] Codegen for FEAT_LRCPC3
Implements support for the following 128-bit atomic operations with +rcpc3:
- 128-bit store-release -> STILP
- 128-bit load-acquire -> LDIAPP
D126250 and D137590
[AArch64] Codegen for FEAT_LRCPC3
Implements support for the following 128-bit atomic operations with +rcpc3:
- 128-bit store-release -> STILP
- 128-bit load-acquire -> LDIAPP
D126250 and D137590 added support for emitting LDAPR (Load-Acquire RCPc) rather
than LDAP (Load-Acquire) when +rcpc is available. This patch allows emitting
the 128-bit RCPc instructions added in FEAT_LRCPC3 (LDIAPP/STILP). The
implementation is different from LDAPR, because there are no non-RCPc
equivalents for these new instructions.
Support for the offset variants will be added in D141431.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D141429
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Revision tags: llvmorg-17-init, llvmorg-15.0.7 |
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| #
f3fb9739 |
| 06-Dec-2022 |
Tomas Matheson <tomas.matheson@arm.com> |
[AArch64] Comprehensive tests for atomic operations
There are a lot of variants of atomic operations, and AArch64 has several
distinct options to codegen them, and does different things depending on
[AArch64] Comprehensive tests for atomic operations
There are a lot of variants of atomic operations, and AArch64 has several
distinct options to codegen them, and does different things depending on
available features, architecture version and optimisation level. The current
testing for atomic operations has been added gradually over time and does not
give full coverate. Given how complex the codegen for atomic operations is, it
is valuable to cover the entire parameter space, i.e. test them all. The
resulting set of tests serve also as a reference for how each is codegened.
In order to keep the test files readable and avoid constant updating for
unrelated codegen changes, the test outputs are filtered to only include the
relevant instructions. This shows for each operation and feature which codegen
approach is taken (e.g. ll/sc loop, atomic instruction, library call).
The following parameter space is tested:
- feature: +lse, +rcpc, etc
- optimisation level: O0, O1 (covers GISel and SelectionDAG)
- atomic instruction: load, store, cmpxchg, atomirmw*
- size: i8, i16, i32, i64, i128
- aligned/unaligned accesses
- endianness: big, little
- atomic ordering: release, acquire, etc
- load atomic only: const/non-const
- cmpxchg only: weak/strong
- atomicrmw: update operation (add, sub, etc)
Notably not covered:
- volatility: there should be no difference between volatile/non-volatile
- atomicrmw fadd/fsub
The files are split by triple, LLVM instruction, and feature. This makes it
easy to diff between features and endianness for a given instruction.
The file that generates the tests is included.
There are 70 test files with an average of 2800 lines each.
Differential Revision: https://reviews.llvm.org/D141064
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