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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1 |
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400b725c |
| 20-Sep-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC
It looks like they were added to prevent fixed length vectors from being expanded, but that's no longer the case today: https://rev
[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC
It looks like they were added to prevent fixed length vectors from being expanded, but that's no longer the case today: https://reviews.llvm.org/D121447#3376520
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Revision tags: llvmorg-19.1.0 |
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89c10e27 |
| 12-Sep-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Add zvfhmin cost model test coverage. NFC
This adds tests coverage for zvfhmin and halfs in general in the cost model tests.
Some existing half tests were split into separate functions so t
[RISCV] Add zvfhmin cost model test coverage. NFC
This adds tests coverage for zvfhmin and halfs in general in the cost model tests.
Some existing half tests were split into separate functions so that if the check prefixes diverge it won't affect the rest of the non-half instructions.
Whilst we're here, also remove the redundant -riscv-vector-bits-min=128 and declares.
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Revision tags: llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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475890cd |
| 04-Jan-2024 |
Shih-Po Hung <shihpo.hung@sifive.com> |
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)
Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)
Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.
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9c39d9bb |
| 28-Dec-2023 |
Vitaly Buka <vitalybuka@google.com> |
Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)
Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629
Issue #76535
This reverts com
Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)
Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629
Issue #76535
This reverts commit 3e75dece919511e4a2edada82d783304cc14a9cd.
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3e75dece |
| 28-Dec-2023 |
Shih-Po Hung <shihpo.hung@sifive.com> |
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)
…Kind
Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of Cos
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)
…Kind
Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2 |
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0a5d52a7 |
| 25-Sep-2023 |
Sergey Kachkov <109674256+skachkov-sc@users.noreply.github.com> |
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.
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Revision tags: llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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3055c581 |
| 19-Jul-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Differential Revision: h
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Differential Revision: https://reviews.llvm.org/D155668
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
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8865ed4d |
| 03-Apr-2023 |
Philip Reames <preames@rivosinc.com> |
[RISCV][TTI] Cost SK_Tranpose as a generic two element shuffle
This matches the actual lowering. The previous costing was "as if" it had been fully scalarized.
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b0ba8fe6 |
| 03-Apr-2023 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Add cost and lowering tests for "transpose" shuffle kinds
These just hit the generic two argument shuffle lowering right now, but that's not how their costed.
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