[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

Patch adds usage of processShuffleMasks in TTI for RISCV. This function is already used for X86
shuffles estimat

[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

Patch adds usage of processShuffleMasks in TTI for RISCV. This function is already used for X86
shuffles estimations and in DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE
functions and in RISCV codegen.
Patch allows better cost estimation for sparse masks and unifies
cost/codegen between different targets/passes

Reviewers: preames

Reviewed By: preames

Pull Request: https://github.com/llvm/llvm-project/pull/118103

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[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

It looks like they were added to prevent fixed length vectors from
being expanded, but that's no longer the case today:
https://rev

[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC

It looks like they were added to prevent fixed length vectors from
being expanded, but that's no longer the case today:
https://reviews.llvm.org/D121447#3376520

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[RISCV] Add cost model coverage for fixed vector insert with known VLEN

[RISCV] Adjust select shuffle cost to reflect mask creation cost (#77963)

This is inspired by
https://github.com/llvm/llvm-project/pull/77342#pullrequestreview-1814673242,
and is split off of same

[RISCV] Adjust select shuffle cost to reflect mask creation cost (#77963)

This is inspired by
https://github.com/llvm/llvm-project/pull/77342#pullrequestreview-1814673242,
and is split off of same with some differences in style.

A select is a vmerge.vv with the additional cost of materializing the
bitmask vector in a vreg. All masks fit within a single vector register
(e8 + m8 is the worst case), and thus our worst case cost should be
roughly 3 (2 scalar to produce the address, one vector load op). Given
most shuffles are small, and the mask will be instead produced by
LUI/ADDI + vmv.s.x or ADDI + vmv.s.x, using 2 as the default seems quite
reasonable. At worst, we're not going to be off by much.

The prior lowering scaled the cost of the bitmask with LMUL, which I
don't understand. At m1 it did use the same base cost of 2. (@lukel97
You wrote the original code here, anything I'm missing here?)

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[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.

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Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)

Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629

Issue #76535

This reverts com

Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)

Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629

Issue #76535

This reverts commit 3e75dece919511e4a2edada82d783304cc14a9cd.

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[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)

…Kind

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of Cos

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)

…Kind

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.

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[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and

[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.

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[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Differential Revision: h

[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Differential Revision: https://reviews.llvm.org/D155668

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[IR] Change shufflevector undef mask to poison

With this patch an undefined mask in a shufflevector will be printed as poison.
This change is done to support the new shufflevector semantics
for unde

[IR] Change shufflevector undef mask to poison

With this patch an undefined mask in a shufflevector will be printed as poison.
This change is done to support the new shufflevector semantics
for undefined mask elements.

Differential Revision: https://reviews.llvm.org/D149210

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[RISCV] Add tests for extract/insert subvector costs and extract lowering