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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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3a26feb6 |
| 06-Nov-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)
In preparation for allowing zvfhmin and zvfbfmin in
isLegalElementTypeForRVV, this lowers fixed-length masked gathers and
[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)
In preparation for allowing zvfhmin and zvfbfmin in
isLegalElementTypeForRVV, this lowers fixed-length masked gathers and
scatters
We need to mark f16 and bf16 as legal in isLegalMaskedGatherScatter
otherwise ScalarizeMaskedMemIntrin will just scalarize them, but we can
move this back into isLegalElementTypeForRVV afterwards.
The scalarized codegen required #114938, #114927 and #114915 to not
crash.
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0 |
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89c10e27 |
| 12-Sep-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Add zvfhmin cost model test coverage. NFC
This adds tests coverage for zvfhmin and halfs in general in the cost model tests.
Some existing half tests were split into separate functions so t
[RISCV] Add zvfhmin cost model test coverage. NFC
This adds tests coverage for zvfhmin and halfs in general in the cost model tests.
Some existing half tests were split into separate functions so that if the check prefixes diverge it won't affect the rest of the non-half instructions.
Whilst we're here, also remove the redundant -riscv-vector-bits-min=128 and declares.
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Revision tags: llvmorg-19.1.0-rc4 |
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e29c5f38 |
| 30-Aug-2024 |
Elvis Wang <110374989+ElvisWang123@users.noreply.github.com> |
[RISCV][TTI] Add legality check of vector of address for gather/scatter. (#106481)
This patch add a legality check that checks if target machine support
vector of address in `isLegalMaskedGatherSca
[RISCV][TTI] Add legality check of vector of address for gather/scatter. (#106481)
This patch add a legality check that checks if target machine support
vector of address in `isLegalMaskedGatherScatter()`.
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2 |
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0a5d52a7 |
| 25-Sep-2023 |
Sergey Kachkov <109674256+skachkov-sc@users.noreply.github.com> |
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.
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Revision tags: llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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3055c581 |
| 19-Jul-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Differential Revision: h
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Differential Revision: https://reviews.llvm.org/D155668
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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68c50b11 |
| 15-Dec-2022 |
Nikita Popov <npopov@redhat.com> |
[CostModel] Convert some tests to opaque pointers (NFC)
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3 |
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4d875910 |
| 18-Aug-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Use VScaleForTuning in costing of operations whose cost depends on VL
On known hardware, reductions, gather, and scatter operations have execution latencies which correlated with the vector
[RISCV] Use VScaleForTuning in costing of operations whose cost depends on VL
On known hardware, reductions, gather, and scatter operations have execution latencies which correlated with the vector length (VL) of the operation. Most other operations (e.g. simply arithmetic) don't correlated in this way, and instead essentially fixed cost as VL varies.
When I'd implemented initial scalable cost model support for reductions, gather, and scatter operations, I had used an upper bound on the statically unknown VL. The argument at the time was that this prevented falsely low costs, and biased the vectorizer away from generating bad (on some hardware) code. Unfortunately, practical experience shows we were a bit too effective at that goal, and the high costs defacto prevents vectorization using these constructs at all.
This patch reverses course, and ties the returned cost not to the maximum possible VL, but the VL which would correspond to VScaleForTuning. This parameter is the same one the vectorizer uses when normalizing loop costs, so the term effectively cancels out. The result is that the vectorizer now sees these constructs as comparable in cost to their fixed length variants.
This does introduce the possibility of the cost for these operations being a significant under estimate on platforms where actual VLEN is far from that implied by VScaleForTuning. On such platforms, we might make poor heuristic choices. Probably not in LV itself (due to the cancellation mentioned above), but possibly during e.g. lowering. I'm not currently aware of any concrete examples of this, but this patch does open a concern which did not previously exist.
Previously, we had the problem of overestimating costs causing the same problem on machines much closer to default values for vscale for tuning. With this patch, we still have that problem potentially if vscale for tuning is set high (manually), and then the code is run on a narrow VLEN machine.
Differential Revision: https://reviews.llvm.org/D131519
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4178e334 |
| 10-Aug-2022 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[CostModel] Update RUN -passes=* to double quotes to appease update scripts on windows
DOS really doesn't like `` quotes to be used in command lines
Some prep work as I'm intending to resurrect D79
[CostModel] Update RUN -passes=* to double quotes to appease update scripts on windows
DOS really doesn't like `` quotes to be used in command lines
Some prep work as I'm intending to resurrect D79483 soon
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Revision tags: llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6 |
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0aebd1d8 |
| 20-Jun-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Fix crash when costing scalable gather/scatter of pointer
This was a bug introduced in d764aa. A pointer type is not a primitive type, and thus we were ending up dividing by zero when comput
[RISCV] Fix crash when costing scalable gather/scatter of pointer
This was a bug introduced in d764aa. A pointer type is not a primitive type, and thus we were ending up dividing by zero when computing VLMax.
Differential Revision: https://reviews.llvm.org/D128219
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d764aa7f |
| 16-Jun-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Add cost model for scalable scatter and gather
The costing we use for fixed length vector gather and scatter is to simply count up the memory ops, and multiply by a fixed memory op cost. For
[RISCV] Add cost model for scalable scatter and gather
The costing we use for fixed length vector gather and scatter is to simply count up the memory ops, and multiply by a fixed memory op cost. For scalable vectors, we don't actually know how many lanes are active. Instead, we have to end up making a worst case assumption on how many lanes could be active. In the generic +V case, this results in very high costs, but we can do better when we know an upper bound on the VLEN.
There's some obvious ways to improve this - e.g. using information about VL and mask bits from the instruction to reduce the upper bound - but this seems like a reasonable starting point.
The resulting costs do bias us pretty strongly away from generating scatter/gather for generic +V. Without this, we'd be returning an invalid cost and thus definitely not vectorizing, so no major change in practical behavior expected.
Differential Revision: https://reviews.llvm.org/D127541
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679aa92d |
| 10-Jun-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Minor test improvements for scalable scatter/gather tests added in 275b2e524
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| #
275b2e52 |
| 10-Jun-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Add cost model coverage for scalable scatter/gather
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