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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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8b55162e |
| 29-Oct-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Add cost model tests for scalable FP reductions. NFC
There are already some in reduce-scalable-fp.ll but this makes it a bit easier to see the difference alongside their fixed-length counter
[RISCV] Add cost model tests for scalable FP reductions. NFC
There are already some in reduce-scalable-fp.ll but this makes it a bit easier to see the difference alongside their fixed-length counterparts.
show more ...
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Revision tags: llvmorg-19.1.3 |
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4c894730 |
| 15-Oct-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Fix bf16 cost model tests. NFC
These were inadvertently changed in #112393
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Revision tags: llvmorg-19.1.2 |
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20864d2c |
| 06-Oct-2024 |
Luke Lau <luke@igalia.com> |
[ValueTypes][RISCV] Add v1bf16 type (#111112)
When trying to add RISC-V fadd reduction cost model tests for bf16, I
noticed a crash when the vector was of <1 x bfloat>.
It turns out that this wa
[ValueTypes][RISCV] Add v1bf16 type (#111112)
When trying to add RISC-V fadd reduction cost model tests for bf16, I
noticed a crash when the vector was of <1 x bfloat>.
It turns out that this was being scalarized because unlike f16/f32/f64,
there's no v1bf16 value type, and the existing cost model code assumed
that the legalized type would always be a vector.
This adds v1bf16 to bring bf16 in line with the other fp types.
It also adds some more RISC-V bf16 reduction tests which previously
crashed, including tests to ensure that SLP won't emit fadd/fmul
reductions for bf16 or f16 w/ zvfhmin after #111000.
show more ...
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| #
3b0e1203 |
| 03-Oct-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Add tests for @llvm.vector.reduce.fmul. NFC
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