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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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c3edeaa6 |
| 01-Nov-2024 |
LiqinWeng <liqin.weng@spacemit.com> |
[Test] Rename the test function name suffix. NFC (#114504)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1 |
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400b725c |
| 20-Sep-2024 |
Luke Lau <luke@igalia.com> |
[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC
It looks like they were added to prevent fixed length vectors from
being expanded, but that's no longer the case today:
https://rev
[RISCV] Remove -riscv-v-vector-bits-min from cost model tests. NFC
It looks like they were added to prevent fixed length vectors from
being expanded, but that's no longer the case today:
https://reviews.llvm.org/D121447#3376520
show more ...
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Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
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84f24c2d |
| 02-Apr-2024 |
Shih-Po Hung <shihpo.hung@sifive.com> |
[RISCV][TTI] Scale the cost of intrinsic umin/umax/smin/smax with LMUL (#87245)
Use the return type to measure the LMUL size for throughput/latency cost
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Revision tags: llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2 |
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0a5d52a7 |
| 25-Sep-2023 |
Sergey Kachkov <109674256+skachkov-sc@users.noreply.github.com> |
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.
show more ...
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Revision tags: llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4 |
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02045021 |
| 21-Oct-2022 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add missing vscale x 1 cost model entries and tests.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136411
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Revision tags: llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0 |
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53f738ce |
| 25-Aug-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV] Add empirical costs for integer min/max and saturing add/sub
All of these are lowered to a single instruction for all legal vector types.
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40069286 |
| 25-Aug-2022 |
Philip Reames <preames@rivosinc.com> |
[RISCV][CostModel] Add test coverage for all the vectorizable binary intrinsics
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