[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/r

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/

[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:

[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found a

[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>

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[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/risc

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
http

[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/

[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.

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[RISCV] Remove Zvk* dependency checks from RISCVISAInfo::checkDependency.

The Zvk* extensions now imply Zve32x or Zve64x so it shouldn't be
possible to fail these dependency checks.

[RISCV] Fix RISCVBitPositions typo (#110953)

This patch updates `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc

[RISCV] Fix RISCVBitPositions typo (#110953)

This patch updates `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions

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[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
t

[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
than slice thanks to std::string_view::substr.

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[RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() error messages.

[RISCV] Add helper functions to exploit similarity of some RISCVISAInfo::checkDependency() error strings. NFC

[RISCV] Merge some ISA error reporting together and make some errors more precise.

Loop over the extension names that have the same error message.

Print the name of Zvk* extensions instead of 'zvk*

[RISCV] Merge some ISA error reporting together and make some errors more precise.

Loop over the extension names that have the same error message.

Print the name of Zvk* extensions instead of 'zvk*'.

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[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instr

[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.

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[RISCV] Support new groupid/bitmask for cpu_model (#101632)

The spec can be found at
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

1. Add the new extension GroupID/Bitmask with lates

[RISCV] Support new groupid/bitmask for cpu_model (#101632)

The spec can be found at
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

1. Add the new extension GroupID/Bitmask with latest hwprobe key.
2. Update the `initRISCVFeature `
3. Update `EmitRISCVCpuSupports` due to not only group0 now.

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[RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (#99700)

This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
h

[RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (#99700)

This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.

This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins (which
have a much narrower user interface), and the avoidance of false
generality. This change deliberately only handles group 0 extensions
(which happen to be all defined ones today), and avoids the tblgen
changes from that review.

I don't have an environment in which I can actually test this, but @BeMg
has been kind enough to report that this appears to work as expected.

Before this can make it into a release, we need a change such as
https://github.com/llvm/llvm-project/pull/99958. The gcc docs claim that
cpu_support can be called by "normal" code without calling the cpu_init
routine because the init routine will have been called by a high
priority constructor. Our current compiler-rt mechanism does not do
this.

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[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)

The `--print-enabled-extensions` has been introduced in the
https://github.com/llvm/llvm-project/pull/98207 , but it seems

[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)

The `--print-enabled-extensions` has been introduced in the
https://github.com/llvm/llvm-project/pull/98207 , but it seems to be
missing a newline in the end.

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[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.

As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.

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[RISCV] Add ability to list extensions enabled for a target (#98207)

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this o

[RISCV] Add ability to list extensions enabled for a target (#98207)

bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option. This patch
adds documentation for this option.

`riscvExtensionsHelp` is renamed to `printSupportedExtensions` to by
synonymous with AArch64 and so it is clear what that function does.

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[RISCV] Don't expose any constructors of RISCVISAInfo publicly. (#98249)

lld was using RISCVISAInfo(unsigned XLen,
RISCVISAUtils::OrderedExtensionMap &Exts). This required a call to
RISCVISAInfo::

[RISCV] Don't expose any constructors of RISCVISAInfo publicly. (#98249)

lld was using RISCVISAInfo(unsigned XLen,
RISCVISAUtils::OrderedExtensionMap &Exts). This required a call to
RISCVISAInfo::postProcessAndChecking to validate the RISCVISAInfo that
was created. This exposes too much about RISCVISAInfo to lld.

Replace with a new RISCVISAInfo::createFromExtMap that is responsible
for creating the object and calling postProcessAndChecking.

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[RISCV] Merge the Arch and Exts variables in RISCVISAInfo::parseArchString. NFC