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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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dfe43bd1 |
| 09-Nov-2024 |
Kazu Hirata <kazu@google.com> |
[X86] Remove unused includes (NFC) (#115593)
Identified with misc-include-cleaner.
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3 |
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| #
e9f9467d |
| 23-Apr-2023 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[X86] X86FixupInstTunings - add VPERMILPDri -> VSHUFPDrri mapping
Similar to the original VPERMILPSri -> VSHUFPSrri mapping added in D143787, replacing VPERMILPDri -> VSHUFPDrri should never be any
[X86] X86FixupInstTunings - add VPERMILPDri -> VSHUFPDrri mapping
Similar to the original VPERMILPSri -> VSHUFPSrri mapping added in D143787, replacing VPERMILPDri -> VSHUFPDrri should never be any slower and saves an encoding byte.
The sibling VPERMILPDmi -> VPSHUFDmi mapping is trickier as we need the same shuffle mask in every lane (and it needs to be adjusted) - I haven't attempted that yet but we can investigate it in the future if there's interest.
Fixes #61060
Differential Revision: https://reviews.llvm.org/D148999
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23472766 |
| 23-Apr-2023 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[X86] X86FixupInstTuning.cpp - fix comment in ProcessVPERMILPSri. NFC.
PERMILPS is only available on AVX or later (VEX/EVEX encoding)
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Revision tags: llvmorg-16.0.2 |
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| #
d6572065 |
| 10-Apr-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Add inst fixup for `unpckps` -> `unpckdq`.
`unpckps` has the same performance as `unpckpd` (only port5) wereas
`unpckdq` can run on p15 on some newer architectures.
`unpckdq` is in the intege
[X86] Add inst fixup for `unpckps` -> `unpckdq`.
`unpckps` has the same performance as `unpckpd` (only port5) wereas
`unpckdq` can run on p15 on some newer architectures.
`unpckdq` is in the integer domain, so only do the transform if the
target has no bypass delay on shuffles (SKL+).
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D147729
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c3f01f13 |
| 10-Apr-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Add inst fixup for `unpckpd` -> `unpckqdq`.
`unpckqdq` seems to be treated as a shuffle from bypass delay
perspective (which makes sense it appears to have shared shuffle units
for all micro-a
[X86] Add inst fixup for `unpckpd` -> `unpckqdq`.
`unpckqdq` seems to be treated as a shuffle from bypass delay
perspective (which makes sense it appears to have shared shuffle units
for all micro-arch).
`unpckqdq` is slightly preferable to `shufpd` as it saves 1-byte of
code size and can be used to replace the micro-fused `rm` version. So,
if the target has no bypass delay, we should do `unpckpd` ->
`unpckqdq` instead of `shufpd.
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D147728
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| #
2ce1698a |
| 10-Apr-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Fix perf bug in `permilps` -> `shufd` in X86FixupInstTuning.
We shouldn't do the transformation if we either have bypass delay OR
the new opcode has worse performance. Previous code was incorr
[X86] Fix perf bug in `permilps` -> `shufd` in X86FixupInstTuning.
We shouldn't do the transformation if we either have bypass delay OR
the new opcode has worse performance. Previous code was incorrectly
using AND.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D147727
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2ffdfb5f |
| 07-Apr-2023 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86] Fix problem in D147541
Differential Revision: https://reviews.llvm.org/D147775
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| #
fd347cea |
| 06-Apr-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Add InstFixup for masked `unpck{l|h}pd` -> masked `shufpd`
This is a follow up D147507 which removed the prior transformation to
`shufps` which was incorrect as the mask was for 64-bit double
[X86] Add InstFixup for masked `unpck{l|h}pd` -> masked `shufpd`
This is a follow up D147507 which removed the prior transformation to
`shufps` which was incorrect as the mask was for 64-bit double
elements, not 32-bit float elements. Using `shufpd` for the
replacement, however, preserves the mask semantics and has the same
benefits as `shufps`.
Reviewed By: pengfei, RKSimon
Differential Revision: https://reviews.llvm.org/D147541
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Revision tags: llvmorg-16.0.1 |
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| #
f7deb69f |
| 04-Apr-2023 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86] Disable masked UNPCKLPD/UNPCKHPD -> SHUFPS transformation
UNPCKLPD/UNPCKHPD is a 64-bit element operation. The masked version
doesn't match SHUFPS in lanes.
This reverts part of D144763.
Revi
[X86] Disable masked UNPCKLPD/UNPCKHPD -> SHUFPS transformation
UNPCKLPD/UNPCKHPD is a 64-bit element operation. The masked version
doesn't match SHUFPS in lanes.
This reverts part of D144763.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D147507
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4 |
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| #
8ac8c579 |
| 08-Mar-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Add masked predicate execution variants for instructions in X86FixupInstTuning
Masked variants of UNPCKLPD, UNPCKHPD, and PERMILPS were missing and
be transformed with the same logic as their
[X86] Add masked predicate execution variants for instructions in X86FixupInstTuning
Masked variants of UNPCKLPD, UNPCKHPD, and PERMILPS were missing and
be transformed with the same logic as their non-masked counterparts.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D144763
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| #
6b29a6f2 |
| 22-Feb-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
[X86] Add support for using Sched/Codesize information to `X86FixupInstTuning` Pass.
Use this to handle new transform: `{v}unpck{l|h}pd` -> `{v}shufps`. We
need the sched information here as `{v}shu
[X86] Add support for using Sched/Codesize information to `X86FixupInstTuning` Pass.
Use this to handle new transform: `{v}unpck{l|h}pd` -> `{v}shufps`. We
need the sched information here as `{v}shufps` is 1 more byte of code
size, so we only want to make this transformation if `{v}shufps` is
actually faster.
Differential Revision: https://reviews.llvm.org/D144570
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Revision tags: llvmorg-16.0.0-rc3 |
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| #
69a322fe |
| 16-Feb-2023 |
Noah Goldstein <goldstein.w.n@gmail.com> |
Add new pass `X86FixupInstTuning` for fixing up machine-instruction selection.
There are a variety of cases where we want more control over the exact
instruction emitted. This commit creates a new p
Add new pass `X86FixupInstTuning` for fixing up machine-instruction selection.
There are a variety of cases where we want more control over the exact
instruction emitted. This commit creates a new pass to fixup
instructions after the DAG has been lowered. The pass is only meant to
replace instructions that are guranteed to be interchangable, not to
do analysis for special cases.
Handling these instruction changes in in X86ISelLowering of
X86ISelDAGToDAG isn't ideal, as its liable to either break existing
patterns that expected a certain instruction or generate infinite
loops.
As well, operating as the MachineInstruction level allows us to access
scheduling/code size information for making the decisions.
Currently only implements `{v}permilps` -> `{v}shufps/{v}shufd` but
more transforms can be added.
Differential Revision: https://reviews.llvm.org/D143787
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