[X86][AVX10.2-BF16] Remove [NE]P from intrinsic and instruction name (#123335)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965

[X86][NFC] Move "_Int" after "k"/"kz" (#121450)

Address comment at
https://github.com/llvm/llvm-project/pull/121373#discussion_r1900402932

[X86] Fix shuffle comment decoding for vinsertps immediate operand (#117009)

The relevant bit from the Intel SDM for vinsertps semantics:
```
IF (SRC = REG) THEN COUNT_S := imm8[7:6] ELSE COUNT_S :=

[X86] Fix shuffle comment decoding for vinsertps immediate operand (#117009)

The relevant bit from the Intel SDM for vinsertps semantics:
```
IF (SRC = REG) THEN COUNT_S := imm8[7:6] ELSE COUNT_S := 0
```

This is now taken into account.

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[X86] Tidyup up AVX512 FPCLASS instruction naming (#116661)

FPCLASS is a unary instruction with an immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using th

[X86] Tidyup up AVX512 FPCLASS instruction naming (#116661)

FPCLASS is a unary instruction with an immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name

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[X86] Emit comments explaining the immediate in vfpclass

This makes the assembly a lot more readable at a glance.

As an example:
```
vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0)
```

[X86] Let's improve the expression we dump for vpternlog

Right now, we are printing stuff like:
zmm0 = (~zmm0 & zmm1 & mem) | (zmm0 & ~zmm1 & ~mem) |
(zmm0 & ~zmm1 & mem) | (zmm0 & zmm1 & ~

[X86] Let's improve the expression we dump for vpternlog

Right now, we are printing stuff like:
zmm0 = (~zmm0 & zmm1 & mem) | (zmm0 & ~zmm1 & ~mem) |
(zmm0 & ~zmm1 & mem) | (zmm0 & zmm1 & ~mem) |
(zmm0 & zmm1 & mem)

This is not wrong but it sure is verbose and it makes it a bit hard to
understand what is going on at a glance.

The above expression is equivalent to:
zmm0 = zmm0 | (zmm1 & mem)

I considered simplifying the expressions on the fly but that gets out of
hand very quickly. Quine-McCluskey is not so simple and so fast that it
makes a ton of sense for our pretty printer. I quickly played around
with some different normal forms and ended up just using this [1] table
of functions with some minor post-processing. I made sure that each
function is identical to the appropriate BooleanFunction in Mathematica.

If the size of these tables ends up mattering for whatever reason there
are a few obvious things we could do to save space without undue effort.

[1]: https://gist.github.com/dougallj/81a80cd381988466c4e1c4889ecac95b#file-2-x86-base-txt

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[X86] Decode VPTERNLOG truth tables when disassembling

Alongside something like:
vpternlogq zmm0, zmm2, zmm1, 64

We will now have a comment on the right like:
# zmm0 = zmm0 & zmm2 & ~zmm1

[X86] Decode VPTERNLOG truth tables when disassembling

Alongside something like:
vpternlogq zmm0, zmm2, zmm1, 64

We will now have a comment on the right like:
# zmm0 = zmm0 & zmm2 & ~zmm1

This makes it easy to tell at a glance what sort of truth table the
instruction will provide.

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[X86] Cleanup AVX512 VBROADCAST subvector instruction names. (#108888)

This patch makes the `VBROADCAST***X**` subvector broadcast instructions consistent - the `***X**` section represents the origi

[X86] Cleanup AVX512 VBROADCAST subvector instruction names. (#108888)

This patch makes the `VBROADCAST***X**` subvector broadcast instructions consistent - the `***X**` section represents the original subvector type/size, but we were not correctly using the AVX512 Z/Z256/Z128 suffix to consistently represent the destination width (or we missed it entirely).

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[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names (#108593)

Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm work

[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names (#108593)

Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on

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[X86] Add missing immediate qualifier to the (V)INSERTPS instruction names (#108568)

Matches (V)BLENDPS etc and makes it easier to algorithmically recreate the instruction name in various analysis s

[X86] Add missing immediate qualifier to the (V)INSERTPS instruction names (#108568)

Matches (V)BLENDPS etc and makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on

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[X86] Use MCRegister in more places. NFC (#108682)

[X86] printExtend - add support for mask predicated instructions

Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can genericall

[X86] printExtend - add support for mask predicated instructions

Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can generically handle the destination + mask register and shuffle mask comment

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[X86] X86FixupVectorConstants - load+zero vector constants that can be stored in a truncated form (#80428)

Further develops the vsextload support added in #79815 / b5d35feacb7246573c6a4ab2bddc4919a4

[X86] X86FixupVectorConstants - load+zero vector constants that can be stored in a truncated form (#80428)

Further develops the vsextload support added in #79815 / b5d35feacb7246573c6a4ab2bddc4919a4228ed5 - reduces the size of the vector constant by storing it in the constant pool in a truncated form, and zero-extend it as part of the load.

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[X86] movsd/movss/movd/movq - add support for constant comments (#78601)

If we're loading a constant value, print the constant (and the zero upper elements) instead of just the shuffle mask.

This

[X86] movsd/movss/movd/movq - add support for constant comments (#78601)

If we're loading a constant value, print the constant (and the zero upper elements) instead of just the shuffle mask.

This did require me to move the shuffle mask handling into addConstantComments as we can't handle this in the MC layer.

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[X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128rm (#75040)

Add missing rm postfix to show these are load instructions

[NFC][X86] Reorder the registers to reduce unnecessary iterations (#70222)

* Introduce field `PositionOrder` for class `Register` and
`RegisterTuples`
* If register A's `PositionOrder` < register

[NFC][X86] Reorder the registers to reduce unnecessary iterations (#70222)

* Introduce field `PositionOrder` for class `Register` and
`RegisterTuples`
* If register A's `PositionOrder` < register B's `PositionOrder`, then A
is placed before B in the enum in X86GenRegisterInfo.inc
* The new order of registers in the enum for X86 will be
1. Registers before AVX512,
2. AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
3. AMX registers (TMM)
4. APX registers (R16-R31)
* Add a new target hook `getNumSupportedRegs()` to return the number of
registers for the function (may overestimate).
* Replace `getNumRegs()` with `getNumSupportedRegs()` in LiveVariables
to eliminate iterations on unsupported registers

This patch can reduce 0.3% instruction count regression for sqlite3
during compile-stage (O3) by not iterating on APX registers
for #67702

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[MC] Use MCRegister instead of unsigned in MCInstPrinter (NFC)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140654

[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC

With C++17 there is no Clang pedantic warning or MSVC C5051.

X86: add newline to end of FMA instruction comments.

The newline is used by Disassembler.cpp (`emitComments`) to work out how to
format them properly, and if there's no newline it goes into an infin

X86: add newline to end of FMA instruction comments.

The newline is used by Disassembler.cpp (`emitComments`) to work out how to
format them properly, and if there's no newline it goes into an infinite loop.

Unfortunately I couldn't get llvm-objdump to be affected, only the MacOS otool
utility which dlopens libLTO.

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[X86][MMX] Remove superfluous 'i' from MMX binop opnames. NFCI.

This is a very old copy+paste typo - none of these binops have an immediate operand.

Noticed while trying to merge MMX instructions i

[X86][MMX] Remove superfluous 'i' from MMX binop opnames. NFCI.

This is a very old copy+paste typo - none of these binops have an immediate operand.

Noticed while trying to merge MMX instructions into some existing SSE instruction scheduler instregex patterns.

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[X86] Move X86ShuffleDecode.cpp/h into MCTargetDesc and remove X86Utils library. NFC

The shuffle decoding is used by X86ISelLowering and
MCTargetDesc/X86InstComments. The latter used to be in a
sepa

[X86] Move X86ShuffleDecode.cpp/h into MCTargetDesc and remove X86Utils library. NFC

The shuffle decoding is used by X86ISelLowering and
MCTargetDesc/X86InstComments. The latter used to be in a
separate InstPrinter library. The Utils library existed to allow
InstPrinter and CodeGen to share the shuffle decoding. Since
X86InstComments now lives in the MCTargetDesc, which CodeGen
already depends on, we can sink the shuffle decoding there as well.

Differential Revision: https://reviews.llvm.org/D77980

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[X86] Print k-mask in FMA3 comments.

Fix "Value stored to 'RegForm' is never read" static analyzer warnings. NFC.

[X86] X86InstComments - add FMA4 comments

These typically match the FMA3 equivalents, although the multiply operands sometimes get flipped due to the FMA3 permute variants.

[X86] Standardize BROADCAST enum names (PR31079)

Tweak EVEX implementation names so it matches the other variants by adding the 'r' prefix. Oddly some of the subvec broadcast ops already matched.